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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 8140729 | Method and apparatus for arbitration on a full-duplex bus using dual phases A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means. ... | 03/20/2012 |
| 7734856 | Method for operating a plurality of arbiters and arbiter system Embodiments related to arbitration are described and depicted. ... | 06/08/2010 |
| 7730247 | Information processing apparatus A bus of a SoC (system on chip) includes a system arbiter for controlling not only a command arbiter but also a read information arbiter, a write data control circuit, a write complete notice arbiter and the like. A sequential table containing a series of system ope... | 06/01/2010 |
| 7631131 | Priority control in resource allocation for low request rate, latency-sensitive units A mechanism for priority control in resource allocation for low request rate, latency-sensitive units is provided. With this mechanism, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it d... | 12/08/2009 |
| 7539806 | Arbitrator and its arbitration method The present invention provides an arbiter and its arbitration method. The master devices in the bus system can be divided into primary master devices and secondary master devices. Said arbiter has first and second stage arbitration modules, wherein the second stage ... | 05/26/2009 |
| 7454546 | Architecture for dynamically reprogrammable arbitration using memory An architecture for a Block RAM (BRAM) based arbiter is provided to enable a programmable logic device (PLD) to efficiently form a memory controller, or other device requiring arbitration. The PLD arbiter provides low latency with a high clock frequency, even when i... | 11/18/2008 |
| 7433989 | Arbitration method of a bus bridge A bus bridge interfaces a primary-side bus with a plurality of secondary-side buses. The primary side bus is a local bus in a system and the secondary-side buses are external buses connected to the system. The bus bridge supports a plurality of kinds of operations o... | 10/07/2008 |
| 7412551 | Methods and apparatus for supporting programmable burst management schemes on pipelined buses Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes on... | 08/12/2008 |
| 7406690 | Flow lookahead in an ordered semaphore management subsystem In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the... | 07/29/2008 |
| 7386645 | System on a chip with an arbitration unit to grant right of access to a common resource in response to conflicting requests for access from initiator modules, and storage key incorporating the arbitration unit An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2≦P≦N and 1≦Q≦N. In the event of a plurality o... | 06/10/2008 |
| 7380038 | Priority registers for biasing access to shared resources A priority register is provided for each of a multiple processor cores of a chip multiprocessor, where the priority register stores values that are used to bias resources available to the multiple processor cores. Even though such multiple processor cores have their... | 05/27/2008 |
| 7373445 | Method and apparatus for allocating bus access rights in multimaster bus systems A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least ... | 05/13/2008 |
| 7370161 | Bank arbiter system which grants access based on the count of access requests Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and al... | 05/06/2008 |
| 7366811 | Bus arbitration system A circuit arrangement, program product and method for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices acc... | 04/29/2008 |
| 7356631 | Apparatus and method for scheduling requests to source device in a memory access system An apparatus and method for scheduling requests to a source device is provided. The apparatus comprises a high-priority request queue for storing a plurality of high-priority requests to the source device; a low-priority request queue for storing a low-priority requ... | 04/08/2008 |
| 7353310 | Hierarchical memory access via pipelining with deferred arbitration A circuit arrangement and method utilize a hierarchical pipelined memory-access structure incorporating deferred arbitration logic. A multi-stage pipelined network defines at least one pipeline between a plurality of initiators and a shared resource. The multi-stage... | 04/01/2008 |
| 7339900 | Method and apparatus for preventing spanning tree loops during traffic overload conditions One embodiment of the present invention provides a system that prevents loops from occurring when spanning tree configuration messages are lost while executing a spanning tree protocol on bridges in a network. During operation, the system executes the spanning tree ... | 03/04/2008 |
| 7337251 | Information processing device with priority-based bus arbitration The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has storage units retaining information representing priorities of the access r... | 02/26/2008 |
| 7328292 | Arbitration method and device In an arbitration device, the entire transfer efficiency is improved without increasing the operating frequency and the number of pins. An overflow monitor mechanism generates an alarm once detecting a danger of occurrence of an overflow in an internal buffer group.... | 02/05/2008 |
| 7324537 | Switching device with asymmetric port speeds In general, in one aspect, the disclosure describes a switching device that includes a plurality of ports. The ports operate at asymmetric speeds. The apparatus also includes a switching matrix to provide selective connectivity between the ports. The apparatus furth... | 01/29/2008 |
| 7315909 | Hierarchized arbitration method An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates i... | 01/01/2008 |
| 7308518 | Interrupt controlling circuit Interrupt controlling circuit by which only a desired one(s) of plural interrupts may readily be masked. An interrupt factor controlling module 105 is provided for each interrupt. An interrupt group setting register 154 holds a group number of an inter... | 12/11/2007 |
| 7305507 | Multi-stage round robin arbitration system Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is configured to partition a plurality of requests into a plurality of bloc... | 12/04/2007 |
| 7302510 | Fair hierarchical arbiter A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request... | 11/27/2007 |
| 7299311 | Apparatus and method for arbitrating for a resource group with programmable weights A system and method for arbitrating for access to a resource group between agents according to a respective programmable weight for each agent. For each agent, a programmable mapping module selectively couples a respective arbitration handshake signal of the agent t... | 11/20/2007 |
| 7296105 | Method and apparatus for configuring an interconnect to implement arbitration Various methods and apparatuses are described in which an interconnect couples to a plurality of initiator network resources and a plurality of target network resources. The interconnect may include a first stage of circuitry, a second stage of circuitry, and an arb... | 11/13/2007 |
| 7269676 | Method and apparatus for controlling an external RF device with a dual processor system A method and apparatus for controlling a device by a serial link from a dual processor system. The configuration of the circuit is simplified and efficiency is enhanced by using independent internal buses and serial link control hardware for each processor and by se... | 09/11/2007 |
| 7263568 | Interrupt system using event data structures Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The Input/Output device writes an event entry into the event data structure in resp... | 08/28/2007 |
| 7257662 | Status reporting apparatus and status reporting method A priority determining unit determines a priority of a status of a device connected to a second bus that is connected, via a bridge, to a first bus to which a central processing unit and a storage unit are connected. A bus-status determining unit determines a use st... | 08/14/2007 |
| 7249210 | Bus access arbitration scheme A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight... | 07/24/2007 |
| 7234012 | Peripheral component interconnect arbiter implementation with dynamic priority scheme A dynamic priority scheme is provided that uses information including the status of the target and data availability in deciding which PCI master should be assigned ownership of the bus. The target uses delayed transactions to complete a read access targeted to it. ... | 06/19/2007 |
| 7231479 | Round robin selection logic improves area efficiency and circuit speed A method and apparatus are provided for efficiently operating a round robin arbitration system in a given computer system. The system utilizes a series of banks of requestors and pointer. The banks of requestors and pointers operate on sequential AND-OR-Inverter/OR-... | 06/12/2007 |
| 7200699 | Scalable, two-stage round robin arbiter with re-circulation and bounded latency A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality ... | 04/03/2007 |
| 7185126 | Universal serial bus hub with shared transaction translator memory Various embodiments of a method and apparatus for implementing multiple transaction translators that share a single memory in a serial hub are disclosed. For example, in one embodiment, a USB (Universal Serial Bus) hub may include a shared memory device, at least on... | 02/27/2007 |
| 7184441 | Network switch stacking configuration A network switch stack configuration includes a first network switch having a plurality of data ports, a first stacking port, and a first CPU interface. A second network switch has a plurality of data ports, a second stacking port, and a second CPU interface. A comm... | 02/27/2007 |
| 7167939 | Asynchronous system bus adapter for a computer system having a hierarchical bus structure A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system bus adapter which includes a local bus adapter for handling transacti... | 01/23/2007 |
| 7149829 | Various methods and apparatuses for arbitration among blocks of functionality Various methods and apparatuses are described in which an arbitration controller cooperates with arbitration logic. The arbitration controller has a plurality of inputs that receive one or more transactions from a plurality of blocks of functionality. The arbitratio... | 12/12/2006 |
| 7146444 | Method and apparatus for prioritizing a high priority client A method and apparatus of deprioritizing a high priority client. An isochronous data stream request is generally referred to as a “high priority” client. These high priority requests are sensitive to time, such that a certain amount of data must be retrieved wit... | 12/05/2006 |
| 7143224 | Smart card for performing advance operations to enhance performance and related system, integrated circuit, and methods An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreov... | 11/28/2006 |
| 7143219 | Multilevel fair priority round robin arbiter A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the r... | 11/28/2006 |
