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| Number | Title | Issue Date |
| 8122175 | Opportunistic transmission of software state information within a link based computing system A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves ... | 02/21/2012 |
| 7809874 | Method for resource sharing in a multiple pipeline environment Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is... | 10/05/2010 |
| 7747806 | Resource use management device, resource use management system, and control method for a resource use management device In a bus arbitration device that utilizes a resource use management device, upon detecting that a processor is permitted to access a memory, a detection unit decreases a counter by 1 and starts a timer, in a delay circuit, that is not in operation to count time. Whe... | 06/29/2010 |
| 7730246 | Opportunistic transmission of software state information within a link based computing system A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves ... | 06/01/2010 |
| 7461191 | Segmented on-chip memory and requester arbitration A memory access technique is provided that may be used in WLAN (Wireless Local Area Network) communication devices. An on-chip memory has multiple memory circuits forming individually addressable memory segments. An arbitration unit arbitrates between multiple reque... | 12/02/2008 |
| 7373445 | Method and apparatus for allocating bus access rights in multimaster bus systems A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least ... | 05/13/2008 |
| 7370135 | Band configuration agent for link based computing system A method is described that involves directing a configuration request through a switch core to a configuration agent. The method also involves processing the configuration request at the configuration agent. The method also involves sending a configuration command d... | 05/06/2008 |
| 7363195 | Methods of configuring a sensor network A sensor network collects time-series data from a process tool and supplies the data to an analysis system where pattern analysis techniques are used to identify structures and to monitor subsequent data based on analysis instructions or a composite model. Time-seri... | 04/22/2008 |
| 7356666 | Local memory management system with plural processors An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third loc... | 04/08/2008 |
| 7334030 | Method and apparatus for the addition and removal of nodes from a common interconnect An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect i... | 02/19/2008 |
| 7328232 | Distributed multiprocessing system A distributed multiprocessing system includes a number of nodes 1-6 interconnected through a central signal routing hub. Each of the nodes 1-6 are preferably connected to an actuator and include a processor for processing information. The... | 02/05/2008 |
| 7328292 | Arbitration method and device In an arbitration device, the entire transfer efficiency is improved without increasing the operating frequency and the number of pins. An overflow monitor mechanism generates an alarm once detecting a danger of occurrence of an overflow in an internal buffer group.... | 02/05/2008 |
| 7310592 | Method and apparatus to group sets of computers into classes for statistical analysis A method of grouping sets of computers into a single class for statistical analysis is disclosed. The method may look at various factors to create equivalent classes of computers depending on the level of aggregation desired which then may be used to provide additio... | 12/18/2007 |
| 7308540 | Pseudo multiport data memory has stall facility A computer memory arrangement comprises a first plurality of input port facilities that are collectively coupled through a first router facility to selectively feed a first plurality of memory modules. It furthermore includes an output port facility that is fed coll... | 12/11/2007 |
| 7287649 | System on a chip for packet processing A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interfa... | 10/30/2007 |
| 7281066 | Memory access system including support for multiple bus widths A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coup... | 10/09/2007 |
| 7277897 | Dynamic reassignment of data ownership Various techniques are described for improving the performance of a shared-nothing database system in which at least two of the nodes that are running the shared-nothing database system have shared access to a disk. Specifically, techniques are provided for changing... | 10/02/2007 |
| 7277982 | DRAM access command queuing structure Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecuti... | 10/02/2007 |
| 7251702 | Network controller and method of controlling transmitting and receiving buffers of the same In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the o... | 07/31/2007 |
| 7234012 | Peripheral component interconnect arbiter implementation with dynamic priority scheme A dynamic priority scheme is provided that uses information including the status of the target and data availability in deciding which PCI master should be assigned ownership of the bus. The target uses delayed transactions to complete a read access targeted to it. ... | 06/19/2007 |
| 7231478 | Programmed access latency in mock multiport memory A computer memory arrangement comprises a first plurality of input port facilities (17–19) that are collectively coupled through a first router facility (32) to selectively feed a second plurality of memory modules (20–24). It furthermore co... | 06/12/2007 |
| 7219128 | Arbitration of state changes An arbitration process ensures changes made by more than one node to the same data are propagated to each node holding the shared entity and applied in the same order on each node. An arbitration cycle for a particular entity is begun on a node (“instigator”) wh... | 05/15/2007 |
| 7206810 | Arbitration of state changes When multiple nodes in a computer network perform work on a shared entity, such as a database record, an arbitration process is used to ensure changes made by more than one node to the same data is propagated to each of the nodes holding the shared entity and that t... | 04/17/2007 |
| 7194518 | Methods and systems for managing state changes during an arbitration cycle when multiple computer nodes request changes of shared data When multiple nodes in a computer network perform work on a shared entity, an arbitration process is used to ensure changes made by more than one node to the same data is propagated to each of the nodes holding the shared entity and that the changes are applied in t... | 03/20/2007 |
| 7174406 | System and method for arbitrating access to a shared resource A system for arbitrating access to a shared resource includes a plurality of microprocessors, a shared resource; and a controller coupled to the plurality of microprocessors and the shared resource by a first bus and a second bus, respectively, the controller includ... | 02/06/2007 |
| 7171526 | Memory controller useable in a data processing system One embodiment relates to a memory controller using an independent memory controller bus in order to transfer data between two or more memories. One embodiment of a data processing system includes a system bus, a system bus master coupled to the system bus, a first ... | 01/30/2007 |
| 7167900 | Methods and systems for managing state changes during an arbitration cycle when multiple computer nodes request changes of shared data When multiple nodes in a computer network perform work on a shared entity, an arbitration process is used to ensure changes made by more than one node to the same data is propagated to each of the nodes holding the shared entity and that the changes are applied in t... | 01/23/2007 |
| 7162557 | Competition arbitration system A competition arbitration system in which chances for using a resource of a computer such as a bus or the like among devices are fair is provided. Pulses are sequentially generated periodically from a pulse generating circuit. It is assumed that first device outputt... | 01/09/2007 |
| 7155576 | Pre-fetching and invalidating packet information in a cache memory A technique for managing a cache memory coupled to an intermediate node's processor. Packets acquired by the intermediate node that are destined for processing by the processor are tracked, without the processor's intervention, to determine if the processor is laggi... | 12/26/2006 |
| 7133949 | Distributed switching method and apparatus Switching method and apparatus for assigning a communication grant to a first processing unit in a communication network comprising a plurality of processing units, each processing unit being connected to each other processing unit of the plurality of processing uni... | 11/07/2006 |
| 7130947 | Method of arbitration which allows requestors from multiple frequency domains The present invention provides a method of arbitration for resources which allows requestors from multiple frequency domains. Most requestors generate requests at full speed. A small number of low-speed requesters generate requests every two full-speed cycles, and h... | 10/31/2006 |
| 7130946 | Configuration and method having a first device and a second device connected to the first device through a cross bar A configuration and method for operating the configuration includes first and second devices connected to one another through a cross bar and accessing one another through the cross bar for reading and/or writing data. When a read access to the second device occurs,... | 10/31/2006 |
| 7124410 | Distributed allocation of system hardware resources for multiprocessor systems A method is provided for allocating system resources across multiple nodes of a system communicating through a hardware device. The method provides for allocation of transaction units or identifiers in an allocating component for use in a multiple target component w... | 10/17/2006 |
| 7124224 | Method and apparatus for shared resource management in a multiprocessing system In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. ... | 10/17/2006 |
| 7120715 | Priority arbitration based on current task and MMU A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priori... | 10/10/2006 |
| 7117281 | Circuit, system, and method for data transfer control for enhancing data bus utilization In a system having a plurality of bus masters, system and method for enhancing data bus utilization are disclosed. This system comprises: a data bus connected to a peripheral apparatus and composed of a plurality of unit data buses each capable of carrying out data ... | 10/03/2006 |
| 7103586 | Collision avoidance in database replication systems Database replication systems replicate blocks of transaction steps or operations with synchronous replication, and perform dual writes with queuing and blocking of transactions. Tokens are used to prepare a target database for replication from a source database and ... | 09/05/2006 |
| 7099971 | Arbitration system A system and method wherein a bus arbiter grants access to a bus to bus-coupled clients in order to provide access to a memory resource shared by the clients in response to “address retry” conditions induced by such clients. The bus arbiter provides access to th... | 08/29/2006 |
| 7099974 | Method, apparatus, and system for reducing resource contention in multiprocessor systems A delay interval is calculated for a processor that attempts to reserve a reserved shared resource in a multiprocessing system. The delay interval is based on the relationship of a requesting processor and a reservation holding processor. Each delay interval is uniq... | 08/29/2006 |
| 7073004 | Method and data processing system for microprocessor communication in a cluster-based multi-processor network The address tenure for PCR synchronization operations is redefined to support inclusion of the synchronization data within the address tenure. The bits of a particular field within the address tenure (e.g., the address field) are re-allocated to synchronization data... | 07/04/2006 |
