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| Number | Title | Issue Date |
| 8041851 | Generic DMA memory space mapping In a data processing system having multiple input/output adapters, a DMA memory block is assigned to each adapter. The DMA memory block has a data area and a generic common control area. All adapters have the same translation control entry for the control area. The ... | 10/18/2011 |
| 8006000 | Bridge, processor unit, information processing apparatus, and access control method There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an address conversion table for converting an effective address in... | 08/23/2011 |
| 7984204 | Programmable direct memory access controller having pipelined and sequentially connected stages A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data con... | 07/19/2011 |
| 7941573 | Semiconductor memory device Data transfer bus charging/discharging current is reduced in a semiconductor memory device. In a data transfer device that sequentially transfers bit sequences in parallel through a plurality of buses from a transmit unit 10 to a receive unit 20, the t... | 05/10/2011 |
| 7664890 | System control device A system control device comprises a system LSI section having a plurality of functional blocks, a system control microcomputer section for controlling the control register of each of the functional blocks, an address decoding section for decoding an access address t... | 02/16/2010 |
| 7603490 | Barrier and interrupt mechanism for high latency and out of order DMA device A direct memory access (DMA) device includes a barrier and interrupt mechanism that allows interrupt and mailbox operations to occur in such a way that ensures correct operation, but still allows for high performance out-of-order data moves to occur whenever possibl... | 10/13/2009 |
| 7594042 | Effective caching mechanism with comparator coupled to programmable registers to store plurality of thresholds in order to determine when to throttle memory requests A system includes a plurality of bus masters that generate direct memory access requests to access a protected memory device. Before granting the access, the system checks for memory protection information stored in a cache. The cache is shared by the bus masters an... | 09/22/2009 |
| 7546394 | Management of configuration data by generating a chain description data set that specifies an order of configuration chain for multi-device systems Methods and apparatus are disclosed for managing configuration data for a system. In various embodiments, a chain description data set is generated to specify an order in a configuration chain of configurable devices in the system and identify configuration data set... | 06/09/2009 |
| 7475166 | Method and system for fully trusted adapter validation of addresses referenced in a virtual host transfer request A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated... | 01/06/2009 |
| 7444441 | Device including means for transferring information indicating whether or not the device supports DMA A device for attachment to a host for serial data communication including means for transferring to the host a predetermined data structure indicating whether or not the device supports direct memory access. ... | 10/28/2008 |
| 7437487 | Storage medium array controller, a storage medium array apparatus, a storage medium drive, a method of controlling a storage medium array, and a signal-bearing medium embodying a program of a storage medium array controller A storage medium drive is controllable by a storage medium array controller. the storage medium array controller receives a data storage medium drive information and the storage medium array controller sets a data transmission parameter with respect to the storage m... | 10/14/2008 |
| 7428603 | System and method for communicating with memory devices via plurality of state machines and a DMA controller The disclosure is directed to a device including a memory interface. The memory interface includes a data interface, a first state machine and a second state machine. The first state machine includes a first chip select interface and a first ready/busy interface. Th... | 09/23/2008 |
| 7418537 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 08/26/2008 |
| 7415035 | Device driver access method into a virtualized network interface A method for providing access to a network interface having a plurality of memory access channels is disclosed. The network interface provides access to a plurality of processing entities. The method includes providing a network interface software hierarchy wherein ... | 08/19/2008 |
| 7415592 | Ring-buffer based buffering apparatus and method of using memory apparatus In a buffering apparatus for digital data for temporarily storing input data and then outputting, a memory apparatus is provided with a plurality of storage areas assigned consecutive identification numbers. A partition designation unit generates an instruction for ... | 08/19/2008 |
| 7415550 | System and method for controlling DMA data transfer A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transf... | 08/19/2008 |
| 7409670 | Scheduling logic on a programmable device implemented using a high-level language Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A portion of a program written in a high-level language is automatically selected for hardware acce... | 08/05/2008 |
| 7404015 | Methods and apparatus for processing packets including accessing one or more resources shared among processing engines Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets... | 07/22/2008 |
| 7404016 | Enhanced power reduction capabilities for streaming direct memory access engine A streaming direct memory access (DMA) engine is disclosed. The streaming DMA engine includes several power reduction capabilities. A controller throttles the DMA engine according to the system throughput requirement and the system processor operation state. The DMA... | 07/22/2008 |
| 7380115 | Transferring data using direct memory access A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the prima... | 05/27/2008 |
| RE40346 | Method and apparatus for providing single channel communications A UART including a logic unit is disclosed, wherein the logic unit automatically enables or disables the UART receiver port whenever data is being processed by the UART for wireless transmission. More specifically, a logic unit is connected to a data store, to a tra... | 05/27/2008 |
| 7376762 | Systems and methods for direct memory access A system and method for providing direct memory access is disclosed. In a particular embodiment, a direct memory access module is disclosed that includes a memory, a first interface coupled to a processor, and a second interface coupled to a peripheral module. A fir... | 05/20/2008 |
| 7376950 | Signal aggregation The invention features a method for transferring data to programming engines using multiple memory channels, parsing data over at most two channels in the memory channels, and establishing at most two logical states to signal completion of a memory transfer operatio... | 05/20/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363397 | System and method for DMA controller with multi-dimensional line-walking functionality A system and method for a DMA controller with multi-dimensional line-walking functionality is presented. A processor includes an intelligent DMA controller, which loads a line description that corresponds to a shape or line. The intelligent DMA controller moves thro... | 04/22/2008 |
| 7363413 | Method and apparatus for controlling connections of PC cards and a passive-card-adapting card used for connecting one of the PC cards to the apparatus A PC card control apparatus includes a PC card connector, a card detector and an interconnection switching circuit. The PC card connector is configured to provide connections for connecting one of a first PC card compliant with specific card standards and a card-ada... | 04/22/2008 |
| 7356627 | Device identification A data handling device capable of operating in a system in which two or more devices are connected by a data bus for the transmission of communications therebetween, the data bus having two or more data lines and the device having: two or more data bus connectors, e... | 04/08/2008 |
| 7356370 | Data processing circuit, data processing apparatus, data processing method, data processing control method, recording medium on which data processing program is stored and recording medium on which data processing control program is stored A data processing circuit is disclosed which can process data precisely while the processing load to a controlling source is reduced. An information detection section detects, from within data read out from a buffer memory and having attribute information, the attri... | 04/08/2008 |
| 7350093 | Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th... | 03/25/2008 |
| 7350059 | Managing stack transfers in a register-based processor The present invention is generally directed to a method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage data transfers between processor registers that are configured to emulate a top portion of a stack and memory, which... | 03/25/2008 |
| 7336209 | Method and device for data transmission A method for serially transmitting data between a first and a second station is provided, the first station unidirectionally transmitting at least two signals to the second station on two signal paths. In this method, a shift register is provided in each station, th... | 02/26/2008 |
| 7334056 | Scalable architecture for context execution System, apparatus and method for controlling the movement of data in a data processing system. The apparatus receives commands from at least one protocol engine and generates contexts representing the commands. The contexts are a data structure representing informat... | 02/19/2008 |
| 7330914 | DMA controller, DMA control method and DMA control program The present invention is a DMA controller that accesses a transfer source and a transfer destination of a DMA transfer via a bus, that chains a plurality of data segments in the transfer source according to an instruction by an external initiator, and that performs ... | 02/12/2008 |
| 7328292 | Arbitration method and device In an arbitration device, the entire transfer efficiency is improved without increasing the operating frequency and the number of pins. An overflow monitor mechanism generates an alarm once detecting a danger of occurrence of an overflow in an internal buffer group.... | 02/05/2008 |
| 7324540 | Network protocol off-load engines The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines). ... | 01/29/2008 |
| 7318174 | Systems, methods, and computer readable medium for analyzing memory Techniques are provided for expanding the functionality of live memory analysis commands to analyze a memory dump or other differing memory types. To this end, a live memory command which normally analyzes live memory is modified to invoke a virtual machine. Live me... | 01/08/2008 |
| 7315912 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 01/01/2008 |
| 7310689 | Bypassing disk I/O operations when porting a computer application from one operating system to a different operating system Systems, methods, and computer products that improve the performance of computer-implemented I/O operations for complex applications, such as a database, that are ported to target computer systems that are not tailored to support the high-performance services that m... | 12/18/2007 |
| 7305499 | DMA controller for controlling and measuring the bus occupation time value for a plurality of DMA transfers The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a d... | 12/04/2007 |
| 7302504 | Methods and apparatus for providing data transfer control A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work ind... | 11/27/2007 |
