Bizarre Patents
A new toilet tank assembly aquarium for housing aquatic creatures.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8185672 | Transmission of data bursts on a constant data rate channel A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving processing node is disclosed. The data channel has a defined frame struct... | 05/22/2012 |
| 8176221 | DMA controller A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption. A typical embodiment of the invention is a DMA controller having: a counter for counting time; a counter... | 05/08/2012 |
| 8176220 | Processor-bus-connected flash storage nodes with caching to support concurrent DMA accesses from multiple processors A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor ... | 05/08/2012 |
| 8166212 | Predictive DMA data transfer A compression and storage device comprises: a compressor configured to compress data; a central processing unit (CPU) configured to control storage of the compressed data and to perform at least one additional task; an electronic memory organized as storage blocks e... | 04/24/2012 |
| 8156259 | Memory data transfer method and system A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a third location or third locations. Within the DMA process the data from ... | 04/10/2012 |
| 8151015 | Systems and methods for effecting DMA data transfers Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a second storage section in an information transfer system. The information ... | 04/03/2012 |
| 8151014 | RAID performance using command descriptor block pointer forwarding technique The apparatus in one example may have: at first and second processing devices; at least one sequence of processes for the first and second devices; the at least one sequence having a command forward instruction such that, after the first processing device completes ... | 04/03/2012 |
| 8145804 | Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processin... | 03/27/2012 |
| 8135878 | Method and apparatus for improving throughput on a common bus A bus scheduling device having a group of direct memory access (“DMA”) engines, a group of target modules (“TM”), a read pending memory, and a bus arbiter is disclosed. A common bus, which is coupled with the DMA engines, TMs, and the read pending memory, is... | 03/13/2012 |
| 8131889 | Command queue for peripheral component In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral compon... | 03/06/2012 |
| 8127053 | System and method for peripheral device communications A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that ... | 02/28/2012 |
| 8127052 | Data transfer control device and computer system A data transfer control device includes a control component (DMA controller 5) which acquires a data transfer instruction including, as its parameters, start memory addresses or start input/output addresses and data transfer size of the peripheral devices to ... | 02/28/2012 |
| 8117356 | Direct memory access (DMA) transfer of network interface statistics In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory acce... | 02/14/2012 |
| 8112560 | Controlling complex non-linear data transfers A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plur... | 02/07/2012 |
| 8112559 | Increasing available FIFO space to prevent messaging queue deadlocks in a DMA environment Embodiments of the invention may be used to manage message queues in a parallel computing environment to prevent message queue deadlock. A direct memory access controller of a compute node may determine when a messaging queue is full. In response, the DMA may genera... | 02/07/2012 |
| 8108571 | Multithreaded DMA controller A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in ... | 01/31/2012 |
| 8103809 | Network devices with multiple direct memory access channels and methods thereof A method, computer readable medium, and a system for communicating with networked clients and servers through a network device includes establishing a plurality of direct memory access (DMA) channels across a host system bus over which a plurality of executing appli... | 01/24/2012 |
| 8099530 | Data processing apparatus A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, an... | 01/17/2012 |
| 8099529 | Software based native command queuing utilizing direct memory access transfer context information Systems and methods for performing native command queuing according to the protocol specified by Serial ATA II for transferring data between a disk and system memory are described. Native command queuing context for queued commands is maintained by a host controller... | 01/17/2012 |
| 8099528 | Data filtering using central DMA mechanism A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. ... | 01/17/2012 |
| 8095700 | Controller and method for statistical allocation of multichannel direct memory access bandwidth A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: (1) channel interfaces including respective counters and configured to provide request signals, priority signals and counter value... | 01/10/2012 |
| 8086765 | Direct I/O device access by a virtual machine with memory managed using memory disaggregation Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used ... | 12/27/2011 |
| 8082372 | Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data process... | 12/20/2011 |
| 8078771 | Sending large command descriptor block (CDB) structures in serial attached SCSI (SAS) controller A system for sending large Command Descriptor Block (CDB) structures in a serial attached SCSI (SAS) controller includes a CDB Transmit Block, a CDB Memory, a Context Memory, a Direct Memory Access (DMA) Queue, a Transmit DMA Engine, and a SAS Interface. The CDB Tra... | 12/13/2011 |
| 8073990 | System and method for transferring updates from virtual frame buffers A method and apparatus for transferring data from a first to a second memory of a computer system. The method comprises (i) initializing a descriptor with a description of physical addressing of a first section of a first array of the first memory; (ii) updating a m... | 12/06/2011 |
| 8069279 | Data flow control within and between DMA channels In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stor... | 11/29/2011 |
| 8069280 | Direct memory access apparatus for sending data stored in memory separately from an operation of a main processor and direct memory access method using the same There is provided a direct memory access apparatus and a direct memory access method. The direct memory access apparatus of the present invention comprises: a variable transmission rule map unit for setting a transmission rule with a variable block length and... | 11/29/2011 |
| 8065447 | Method and apparatus for determining priorities in direct memory access device having multiple direct memory access request blocks A priority determining method and apparatus can reduce a total waiting time of DMA request blocks by granting priority to each of Direct Memory Access (DMA) request blocks transmitting a DMA request signal, based on Data Transfer Amounts (DTAs) of the DMA request bl... | 11/22/2011 |
| 8065448 | DMA control system, printing apparatus, transfer instruction method and computer readable medium A DMA control system includes: a plurality of DMA control units that are controlled in a manner that, while one of the plurality of DMA control units use a transmission path, the other DMA control units other than the one of the plurality of DMA control unit are pre... | 11/22/2011 |
| 8065449 | DMA device having plural buffers storing transfer request information and DMA transfer method A Direct Memory Access (DMA) device includes a first buffer which holds a first transfer information required for a first transfer request, and a second buffer which holds a second transfer information required for a second transfer request, and a transfer request c... | 11/22/2011 |
| 8060667 | Apparatus and method for processing high speed data using hybrid DMA An apparatus and a method for processing high speed data using hybrid Direct Memory Access (DMA) are provided. The method includes determining a size of data to be transmitted, determining a memory access method of the data by comparing the determined size of the da... | 11/15/2011 |
| 8046503 | DMA controller, system on chip comprising such a DMA controller, method of interchanging data via such a DMA controller A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local memory, associated with an indication to the local memory of an addres... | 10/25/2011 |
| 8041849 | Method for handling small computer system interface (SCSI) commands via a redundant array of inexpensive disks (RAID) device driver The present invention is a method for handling an operation system kernel-provided command via a software-based device driver. The method includes receiving the operation system kernel-provided command from an operation system kernel. The method further includes det... | 10/18/2011 |
| 8041847 | Periodic and conditional execution of DMA operations Scheduling Direct Memory Access (DMA) operations. Blocks are provided in a first DMA chain, with each block in the first DMA chain corresponding to an operation and comprising a pair of pointers, a first pointer pointing to a command structure to be executed or a da... | 10/18/2011 |
| 8041848 | Media processing method and device A media processing system and device with improved power usage characteristics, improved audio functionality and improved media security is provided. Embodiments of the media processing system include an audio processing subsystem that operates independently of the ... | 10/18/2011 |
| 8041850 | Storage apparatus and data integrity assurance method A channel control unit of a storage apparatus is provided with: a variable-length DMA (Direct Memory Access) that performs data transfer of variable-length data sent to or received from the host computer in accordance with an I/O request; a fixed-length DMA that per... | 10/18/2011 |
| 8037214 | Method and apparatus for controlling direct memory access Provided are a method and apparatus for controlling direct memory access. In the method, data to be transmitted are read and stored in response to a direct memory access controller (DMAC) operation request, and a portion of the data corresponding to an initial burst... | 10/11/2011 |
| 8037216 | DMA transfer control device A DMA transfer control device includes a setting register group for setting transfer informations, a number-of-transfers register to which the number of transfers to be performed is set, and which updates a value thereof every time one DMA transfer is completed, a t... | 10/11/2011 |
| 8037217 | Direct memory access in a hybrid computing environment DMA in a computing environment that includes several computers and DMA engines, the computers adapted to one another for data communications by an data communications fabric, each computer executing an application, where DMA includes: pinning, by a first application... | 10/11/2011 |
| 8037212 | Event notification system and method A technique for user notification involves modifying a title associated with a process to include information about an event that calls for user notification. A method according to the technique may include running a process, processing an event, generating a string... | 10/11/2011 |
