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| Number | Title | Issue Date |
| 8185680 | Method for changing ownership of a bus between master/slave devices A system may comprise multiple master/slave devices coupled to a common bus, where one of the devices may operate as the current master device and the other devices may operate as current slave devices. Current slave devices may embed bus ownership request informati... | 05/22/2012 |
| 8140727 | Bus arbitration apparatus and method A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests wi... | 03/20/2012 |
| 7962678 | Bus arbitration apparatus and method A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests wi... | 06/14/2011 |
| 7849245 | Bus-based communication system A communications bus operates using transition coding, for example NRZI coding, with transition-dominant signalling. That is, when the signal takes a first binary value, binary “1”, the component drives the bus line to its opposite state, and, when the signal ta... | 12/07/2010 |
| 7386750 | Reduced bus turnaround time in a multiprocessor architecture Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus handoff. The method may also include bypassing data from recovery la... | 06/10/2008 |
| 7352708 | Method and apparatus for border node behavior on a full-duplex bus A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method for determining and communicating the existence of a hybrid bus is disclosed. A method for determining a path to a senior border... | 04/01/2008 |
| 7353317 | Method and apparatus for implementing heterogeneous interconnects Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transf... | 04/01/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7353322 | System and method for providing dynamic configuration ROM using double image buffers A dynamic configuration ROM which may be updated while linked to the serial bus and with little or no risk of publishing inconsistent configuration ROM information to the other nodes on the bus. The dynamic configuration ROM comprises first and second configuration ... | 04/01/2008 |
| 7353284 | Synchronized transmission of audio and video data from a computer to a client via an interface A method for controlling data transmission between a computer and a video client via an interface, the method comprising: the computer polling the interface a first time to determine the size of the buffer on the interface; receiving a first buffer size value from t... | 04/01/2008 |
| 7349998 | Bus control system for integrated circuit device with improved bus access efficiency The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI ... | 03/25/2008 |
| 7350002 | Round-robin bus protocol A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the dev... | 03/25/2008 |
| 7343395 | Facilitating resource access using prioritized multicast responses to a discovery request Systems and methods are provided to facilitate resource access using prioritized multicast responses to a discovery request. ... | 03/11/2008 |
| 7340542 | Data processing system with bus access retraction A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of... | 03/04/2008 |
| 7340547 | Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an ... | 03/04/2008 |
| 7337252 | System and method for resolving conflicts of re-locking resources A system for resolving conflicts of re-locking resources includes: a plurality of system resources (10), a memory (11), and a central processing unit (12). The memory includes a data storing region (110), a re-lock resolving module (11... | 02/26/2008 |
| 7330992 | System and method for read synchronization of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 02/12/2008 |
| 7321368 | Electronic system and method for display using a decoder and arbiter to selectively allow access to a shared memory An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the... | 01/22/2008 |
| 7317694 | Method and apparatus for border node behavior on a full-duplex bus A method is disclosed for determining and communicating the existence of a hybrid bus. The method comprises the acts of determining whether the node has a connection to a Legacy link layer; if the node determines that it has a connection to a Legacy link layer, then... | 01/08/2008 |
| 7315913 | CPU system, bus bridge, control method therefor, and computer system In a system having an arrangement that a CPU (101) connected to a bus (107) via bus bridge (103) and a CPU 102 connected to a bus (107) via bus bridge (104), when the bus bridge (103) receives a semaphore acquisition ... | 01/01/2008 |
| 7293206 | Test data pattern for testing a CRC algorithm A method of generating a test data pattern for testing a CRC algorithm, the CRC algorithm configured to generate CRC values based on a generator polynomial, the method including identifying a desired pattern of intermediate CRC values. The method includes generating... | 11/06/2007 |
| 7289165 | Self-directing bus amplifier and method A self-directing bus amplifier and method is disclosed, which includes an input biased at a given voltage level and a tri-state amplifier with a first input terminal coupled to the biased input and an output coupled to an output bus. A field effect transistor with a... | 10/30/2007 |
| 7280491 | Method and apparatus for border node behavior on a full-duplex bus A method relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method is disclosed for determining a path to a senior border node comprising the acts of: determining whether a B PHY has received a Self-ID packet without... | 10/09/2007 |
| 7280490 | Method and apparatus for border node behavior on a full-duplex bus A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method is disclosed for determining a path to a senior border during the Self-ID process in a full-duplex communications system having at leas... | 10/09/2007 |
| 7277952 | Distributed system resource protection via arbitration and ownership In a distributed system, a resource such as a storage device is protected by an owner node's exclusive access to it, wherein exclusive access is established via a persistent reservation on the resource. A persistent reservation is never removed, however the owner no... | 10/02/2007 |
| 7275123 | Method and apparatus for providing peer-to-peer data transfer within a computing environment A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the ... | 09/25/2007 |
| 7266626 | Method and apparatus for connecting an additional processor to a bus with symmetric arbitration A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An additional agent may monitor the symmetric arbitration of the symmetri... | 09/04/2007 |
| 7266617 | Method and apparatus for border node behavior on a full-duplex bus A method for determining and communicating the existence of a hybrid bus is disclosed. The method determines whether a connected node is a border node and forwards isochronous and asynchronous requests if the node is not a border node. If the node is a border node, ... | 09/04/2007 |
| 7260685 | Memory hub and access method having internal prefetch buffers A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history lo... | 08/21/2007 |
| 7251702 | Network controller and method of controlling transmitting and receiving buffers of the same In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the o... | 07/31/2007 |
| 7249236 | Method and system for controlling memory accesses to memory modules having a memory hub architecture A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules... | 07/24/2007 |
| 7246052 | Bus master and bus slave simulation using function manager and thread manager The system simulator comprises master simulators 1f, 1s, 2f and 2s for simulating a bus master, a slave simulator L for simulating a bus slave, a function manager F for sequentially actuating the master simulat... | 07/17/2007 |
| 7243229 | Exclusive access control apparatus and method A computing system and an exclusive access control method are provided for preventing degraded performance of a network caused by exclusive access control, and for permitting a computer to exclusively access a storage area irrespective of whether a storage has an ex... | 07/10/2007 |
| 7237071 | Embedded symmetric multiprocessor system with arbitration control of access to shared resources A single chip, embedded symmetric multiprocessor (ESMP) having parallel multiprocessing architecture composed of identical processors includes a single program memory. Program access arbitration logic supplies an instruction to a single requesting central processing... | 06/26/2007 |
| 7237135 | Cyclemaster synchronization in a distributed bridge A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon occurrence of a cycle synchronization event on the local portal; the pe... | 06/26/2007 |
| 7231467 | Method and apparatus for providing an inter integrated circuit interface with an expanded address range and efficient priority-based data throughput A method and apparatus implementing an enhanced protocol between an I2C master and an I2C slave. In various embodiments the invention permits greater addressability space and high priority access to the slave device. The enhanced protocol is implemented by the addit... | 06/12/2007 |
| 7225284 | Increasing the quantity of I/O decode ranges using SMI traps A method of increasing the quantity of input/output (I/O) decode ranges using system management interrupts (SMI) traps is disclosed. In one aspect, the present disclosure teaches a method of increasing the quantity of I/O decode ranges using SMI traps in a chipset i... | 05/29/2007 |
| 7225286 | Method to measure transmission delay between 1394 bridges In lieu of a strictly dedicated bus transaction such as a ping and self-identification, the timing delays for an IEEE 1394 serial bus are determined by an asynchronous transaction request and responsive acknowledgement response. Timing may therefore be determined ei... | 05/29/2007 |
| 7194564 | Method and apparatus for preventing loops in a full-duplex bus A method and apparatus is disclosed for preventing loops in a full-duplex bus. One method has the acts of: selecting at least two candidates to join said bus; establishing a dominant candidate from one of said at least two candidates; testing for loops in said bus; ... | 03/20/2007 |
| 7191266 | Method and apparatus for supporting and presenting multiple serial bus nodes using distinct configuration ROM images A method and apparatus for presenting a plurality of link devices as separate nodes within a single serial bus module by generating individual or a distinct configuration ROM image for each link device in the module. Each configuration ROM includes an entry for a di... | 03/13/2007 |
