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| Number | Title | Issue Date |
| 7882291 | Apparatus and method for operating plural applications between portable storage device and digital device An apparatus and method for operating many applications between a portable storage device and a digital device are provided. The method includes opening at least two logical channels from the digital device to the portable storage device through a physical channel, ... | 02/01/2011 |
| 7802040 | Arbitration method reordering transactions to ensure quality of service specified by each transaction A method, an interconnect and a system for processing data is disclosed. The method comprises the steps of: a) receiving a request to perform a data transaction between a master unit and a slave unit, b) receiving an indication of a quality of service requirement as... | 09/21/2010 |
| 7734855 | Gap count analysis for the P1394a BUS A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sendin... | 06/08/2010 |
| 7493434 | Determining the value of internal signals in a malfunctioning integrated circuit A method that enables testing any point (target point) within a core, including a point within a combinatorial circuit of a core, permits testing of points that are not otherwise unobservable in normal debugging processes. Such a target point is tested by identifyin... | 02/17/2009 |
| 7487276 | Bus arbitration system A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined se... | 02/03/2009 |
| 7366811 | Bus arbitration system A circuit arrangement, program product and method for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices acc... | 04/29/2008 |
| 7353309 | Bus system, bus manager device, node device, and program for bus manager device In a bus system, in accordance with reservations of transfers of isochronous blocks of data and with requests by the node devices for transfers of ones of the isochronous blocks of data and regular blocks of data, a bus manager generates a schedule of the operating ... | 04/01/2008 |
| 7353308 | Avoiding oscillation in self-synchronous bi-directional communication system In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to... | 04/01/2008 |
| 7343525 | Method and apparatus of detecting error of access wait signal A method and an apparatus for detecting an error of an access wait signal are disclosed. The method comprises the steps of accessing the input/output (I/O) device according to an I/O control command of the electronic device to access the I/O device; and returning to... | 03/11/2008 |
| 7308517 | Gap count analysis for a high speed serialized bus A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sendin... | 12/11/2007 |
| 7305493 | Embedded transport acceleration architecture An apparatus and a system may include an adaptation module, a plurality of Direct Transport Interfaces (DTIs), a DTI accelerator, and a Transport Control Protocol/Internet Protocol (TCP/IP) accelerator. The adaptation module may provide a translated sockets call fro... | 12/04/2007 |
| 7290075 | Performing arbitration in a data processing apparatus An apparatus for arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparat... | 10/30/2007 |
| 7263566 | Method and apparatus of reducing transfer latency in an SOC interconnect Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communi... | 08/28/2007 |
| 7257662 | Status reporting apparatus and status reporting method A priority determining unit determines a priority of a status of a device connected to a second bus that is connected, via a bridge, to a first bus to which a central processing unit and a storage unit are connected. A bus-status determining unit determines a use st... | 08/14/2007 |
| 7249210 | Bus access arbitration scheme A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight... | 07/24/2007 |
| 7225286 | Method to measure transmission delay between 1394 bridges In lieu of a strictly dedicated bus transaction such as a ping and self-identification, the timing delays for an IEEE 1394 serial bus are determined by an asynchronous transaction request and responsive acknowledgement response. Timing may therefore be determined ei... | 05/29/2007 |
| 7222208 | Simultaneous bidirectional port with synchronization circuit to synchronize the port with another port A simultaneous bidirectional port coupled to a bus includes a synchronization circuit that synchronizes the port with another simultaneous data port coupled to the same bus. The synchronization circuit includes an output driver having an imbalanced output impedance,... | 05/22/2007 |
| 7200735 | High-performance hybrid processor with configurable execution units A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and... | 04/03/2007 |
| 7197589 | System and method for providing access to a bus A computer system (10) includes a bus controller (12), a bus (14), a plurality of processing devices (16) and a plurality of enabling switches (18). Each enabling switch (18) corresponds to a separate one of the processing d... | 03/27/2007 |
| 7174401 | Look ahead split release for a data bus A data bus transfers data between at least one slave device and a plurality of master devices, and an arbiter grants access to each of the master devices. The slave device includes look-ahead apparatus that includes staging register for staging an identification of ... | 02/06/2007 |
| 7143224 | Smart card for performing advance operations to enhance performance and related system, integrated circuit, and methods An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreov... | 11/28/2006 |
| 7130943 | Data processing system with bus access retraction A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of... | 10/31/2006 |
| 7107375 | Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology An arbitration elimination scheme for a bus. In a preferred embodiment, a programmable counter determines when a SCSI bus idle condition is reached and when a portion of an arbitration window for the bus has passed without participants. If there are no participants ... | 09/12/2006 |
| 7103691 | Method, system and device for a processor to access devices of different speeds using a standard memory bus A method for accessing a device, such as a memory device and an interface device, by a processor is disclosed. The method involves the processor requesting access permission for the transfer of data. The bridge device grants access permission. The processor in respo... | 09/05/2006 |
| 7099968 | System and method for generating bus requests in advance based on speculation states A system and method predict when to generate a bus request ahead-of-time based on bus-activity, bus-usage efficiency and bus-bandwidth usage. A bus-usage efficiency indicator may be generated by a requester, such as a memory controller, based on a number of unused b... | 08/29/2006 |
| 7099973 | Method and system of bus master arbitration A system (100) having a plurality of bus masters (111–113) coupled to an arbiter (150) is disclosed. An arbiter (150) is coupled to a first storage location (151) and a second storage location (152), where the first and se... | 08/29/2006 |
| 7099972 | Preemptive round robin arbiter A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for resources. Each indicator enables indication of a condition in which the re... | 08/29/2006 |
| 7093256 | Method and apparatus for scheduling real-time and non-real-time access to a shared resource A method and apparatus are provided in a computing environment for scheduling access to a resource. The method grants access to the resource by a non-real-time request when the non-real-time request can be completed before the latest possible start time at which a f... | 08/15/2006 |
| 7043595 | Data transfer control device Even when an S-PCI bus 1b requests transfer while a P-PCI bus 1a is executing burst transfer, assert of a TRDY# signal for data transfer of the P-PCI side is delayed so that next data transfer of the P-PCI side is completed within 8 clock... | 05/09/2006 |
| 6988156 | System and method for dynamically tuning interrupt coalescing parameters A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many packets the interface may accumulate, or how much time the interface may ... | 01/17/2006 |
| 6978330 | Shared resource access via declarations that contain a sequence number of a packet Logic (also called “re-ordering semaphore”) issues semaphore grants to access a shared resource in an order different from the order in which semaphore requests for accessing the shared resource are received. The re-ordering semaphore needs to receive a semaphor... | 12/20/2005 |
| 6976108 | System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter has programmable rankings for assigning priorities to requests from ... | 12/13/2005 |
| 6968431 | Method and apparatus for livelock prevention in a multiprocessor system In a multiprocessor system using snooping protocols, system command conflicts are prevented by comparing processor commands with prior snoops within a specified time defined window. A determination is then made as to whether a command issued by a given processor is ... | 11/22/2005 |
| 6952747 | Method of delaying bus request signals to arbitrate for bus use and system therefor In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the... | 10/04/2005 |
| 6934781 | System and method for effectively performing isochronous data transfers A system and method for effectively performing isochronous data transfers comprises a network device including an input/output (I/O) bus that is coupled to an input/output (I/O) node and an isochronous-capable network interface. The network interface and the I/O nod... | 08/23/2005 |
| 6922423 | Control system for a semiconductor laser A control system architecture that allows a semiconductor laser to be stabilized with respect to critical parameters, such as output power and/or emission wavelength, with a reduced cost with respect to the components required to implement control, while simultaneou... | 07/26/2005 |
| 6917994 | Device and method for automatically generating an appropriate number of wait cycles while reading a nonvolatile memory An interface manages the exchange of information between a bus system and a memory during reading, according to a communication protocol. The interface has a protocol-decoding unit, which receives from outside commands and information for managing the reading and ge... | 07/12/2005 |
| 6910088 | Bus arbitration using monitored windows of time A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the sec... | 06/21/2005 |
| 6895462 | Integrated circuit An integrated circuit includes a processor and at least one module and provides registers required for the modules as well as access to these registers. By concentrating the required registers according to the invention in a central register bank, which like the pro... | 05/17/2005 |
| 6889277 | System and method for dynamically tuning interrupt coalescing parameters A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface to suit the workload of the interface. An interrupt handler adjusts dynamic Packet and/or Latency values of the interface to control how many packets the interf... | 05/03/2005 |
