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| Number | Title | Issue Date |
| 8135893 | System, apparatus and method for granting access to a shared communications bus Systems, apparatuses and methods for timing access to a shared communications bus by a plurality of devices. Each of a plurality of nodes is successively provided an opportunity to gain access to a shared bus according to a time slot allocation referenced from a tim... | 03/13/2012 |
| 8037226 | Time and event based message transmission A system, apparatus and method for making possible more efficient utilization of available band-width on the system's bus connection between, from and/or to modules incorporated in the system and/or reduction of accuracy requirements for clock functions utilized in ... | 10/11/2011 |
| 7949811 | Method and device for creating a time schedule for transmitting messages on a bus system A method for creating a time schedule for transmitting messages on a bus system (bus schedule), the time schedule being created by using a genetic algorithm. ... | 05/24/2011 |
| 7913014 | Data processing system and method for memory arbitration The present invention relates to a data processing system is provided which comprises at least one first processing unit (CPU), at least one second processing unit (PU), at least one memory module (MEM), and an interconnect. The memory module (MEM) serves to store d... | 03/22/2011 |
| 7913015 | Implantable medical device bus system and method A bus system is provided for implantable medical devices. The bus system provides for flexible and reliable communication between subsystems in an implantable medical device. The bus system facilitates a wide variety of communications between various subsystems. The... | 03/22/2011 |
| 7890685 | Multi-core data processor To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bu... | 02/15/2011 |
| 7802039 | Memory controller, bus system, integrated circuit, and control method of integrated circuit including controlling flow of data to and from memory An integrated circuit including: a bus system including a bus master connected to a bus; and a memory controller connected to the bus system and controlling a connection between the bus master and a memory, in which the bus system includes a counter counting a waiti... | 09/21/2010 |
| 7761634 | Method, device and system for exchanging data via a bus system A method for exchanging data in messages between at least two stations connected via a bus system. The messages contain the data being transmitted by the stations over the bus system, and the messages are controlled over time by a first station in such a manner that... | 07/20/2010 |
| 7711880 | Schematizing of messages in distributed control and supervision system In a CAN system, an arrangement is incorporated for making possible more efficient utilization of available band-width on the system's bus connection between, from and/or to modules incorporated in the system and/or reduction of accuracy requirements for clock funct... | 05/04/2010 |
| 7546404 | Method and apparatus for arbitration in a wireless device A method and apparatus for traffic arbitration in a system are provided. In the system, a first module operating in a first protocol and a second module operating in a second protocol share one communication channel. An arbitration circuit schedules medium accesses ... | 06/09/2009 |
| 7444448 | Data bus mechanism for dynamic source synchronized sampling adjust An integrated device for sampling data packets asserted sequentially on a system bus, including a clock input for receiving a bus clock signal, a data bus interface for receiving the data packets and for detecting at least one data strobe indicating data validity, a... | 10/28/2008 |
| 7437495 | Method and apparatus for assigning bus grant requests Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an... | 10/14/2008 |
| 7433984 | Time-based weighted round robin arbiter A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the PCI bus. An arbiter state machine is coupled to the phase table and looks at the port assignment for the... | 10/07/2008 |
| 7430201 | Methods and apparatus for accessing full bandwidth in an asynchronous data transfer and source traffic control system Methods for accessing full bandwidth in an asynchronous data transfer and source traffic control system include permitting some bus users (e.g. networks cards) to access both odd and even frames while permitting other bus users (e.g. subscriber line cards) to access... | 09/30/2008 |
| 7409480 | Electronic equipment, method of receiving data, method of transmitting data, method of setting channel and method of grouping electronic equipment into channels It becomes possible for a user to set a transmission or reception channel arbitrarily and easily. Each of equipment connected to an IEEE 1394 bus may include a register provided within a RAM 113 to thereby set a transmission or reception default channel. If c... | 08/05/2008 |
| 7406552 | Systems and methods for early fixed latency subtractive decoding including speculative acknowledging Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively, or conditionally, acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipe... | 07/29/2008 |
| 7406531 | Method and communication system for data exchange among multiple users interconnected over a bus system A method and a communication system for exchanging data between at least two users interconnected over a bus system are described. The data is contained in messages which are transmitted by the users over the bus system. To improve data exchange among users so that ... | 07/29/2008 |
| 7380034 | Method of arbitration for bus use request and system therefor In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the... | 05/27/2008 |
| 7373445 | Method and apparatus for allocating bus access rights in multimaster bus systems A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least ... | 05/13/2008 |
| 7372768 | Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of... | 05/13/2008 |
| 7366811 | Bus arbitration system A circuit arrangement, program product and method for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices acc... | 04/29/2008 |
| 7366810 | Method and system for multi-processor arbitration A computing system includes one or more buses, a plurality of bus agents, and a chip set. The plurality of bus agents are capable of accessing at least one of the buses. The chipset arbitrates access to a bus for at least two of the bus agents such that utilization ... | 04/29/2008 |
| 7359782 | Vehicular impact reactive system and method System and method for reacting to an expected impact involving a vehicle including an anticipatory sensor system for determining that an impact involving the vehicle is about to occur prior to the impact and an impact responsive system coupled to the sensor system a... | 04/15/2008 |
| 7350003 | Method, system, and apparatus for an adaptive weighted arbiter An adaptive weighted arbitration algorithm that is user configurable is discussed. The arbitration logic and algorithm considers past arbitration history events and is dynamic to allow for losing bidders to increase their probability of being selected to access the ... | 03/25/2008 |
| 7350004 | Resource management device Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessin... | 03/25/2008 |
| 7340545 | Distributed peer-to-peer communication for interconnect busses of a computer system There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to establish an isochronous channel between a first device and a second de... | 03/04/2008 |
| 7337015 | Method and apparatus for controlling digital electronic products A method and an apparatus for controlling a digital electronic product, using a control signal transmitter and a signal receiver combined with a gate system for controlling a digital home appliance, such that a system activation/inactivation control mechanism is est... | 02/26/2008 |
| 7337253 | Method and system of routing network-based data using frame address notification A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existin... | 02/26/2008 |
| 7333822 | Method for transmitting messages in a telecommunication network A method is provided for transmitting messages, for example, in a telecommunications network, in which a first message service and a second message service are available. Dedicated messages of the first message service are sent using messages of the second message s... | 02/19/2008 |
| 7330908 | System and method for processing packets using location and content addressable memories An apparatus and method for enhancing the infrastructure of a network such as the Internet is disclosed. A packet interceptor/processor apparatus is coupled with the network so as to be able to intercept and process packets flowing over the network. Further, the app... | 02/12/2008 |
| 7325082 | System and method for guaranteeing transactional fairness among multiple requesters A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is used to control servicing of multiple requests made by multiple request... | 01/29/2008 |
| 7317734 | Method and apparatus for emulating ethernet functionality over a serial bus Applications can transparently use a bus, such as the IEEE-1394 serial bus, as if it were an Ethernet (IEEE 802.3). In a conventional Ethernet, each node is assigned a unique 6-byte MAC address in order to receive frames addressed to it over the LAN. According to th... | 01/08/2008 |
| 7318144 | Apparatus and method for interconnecting a processor to co-processors using shared memory An apparatus and method for interfacing a processor to one or more co-processors interface provides a dual ported memory to be used as a message passing buffer between the processor and the co-processors. Both the processor and co-processors can connect asynchronous... | 01/08/2008 |
| 7315616 | System and method for maintaining real-time agent information for multi-channel communication queuing An apparatus and method for maintaining data for multi-channel communication queuing associated with different media formats such as telephone, email, and fax. A list of agent data includes information related to types of communication media an agent can access. The... | 01/01/2008 |
| 7313716 | Method and device for exchanging data between at least two stations connected via a bus system A method and a device for exchanging data in messages between at least two stations connected via a bus system, the messages containing the data being transmitted by the stations over the bus system and the messages being controlled over time by a first station in s... | 12/25/2007 |
| 7293126 | Enhanced structure of extensible time-sharing bus capable of reducing pin number, extending memory capacity, and performing I/O mapping access and block access An enhanced structure of extensible time-sharing bus, which essentially uses an address and data bus in time-sharing to send addresses and data between a microprocessor and a memory through a microprocessor interface and a memory interface, and a logic combination o... | 11/06/2007 |
| 7289567 | Apparatus and method for transmitting and receiving data using partial chase combining An apparatus and method for transmitting and receiving data, wherein retransmissions of information can be a different size from the initial transmission. The invention utilizes a partial Chase encoder 306 to truncate or expand data depending on the availabil... | 10/30/2007 |
| 7275119 | Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an address signal to an address input of a multiplexer, to transmit a data... | 09/25/2007 |
| 7274585 | Methods of operating integrated circuit memory devices Methods of operating an integrated circuit memory device include providing a first address and a first command to the memory device and executing the first command within the memory device. This step of executing the first command is performed concurrently with prov... | 09/25/2007 |
| 7260688 | Method and apparatus for controlling access to memory circuitry Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing system. A plurality of ports is respectively coupled to said plurality... | 08/21/2007 |
