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| Number | Title | Issue Date |
| 7716405 | Computer system A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system ... | 05/11/2010 |
| 7315909 | Hierarchized arbitration method An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates i... | 01/01/2008 |
| 7181557 | Single wire bus for connecting devices and methods of operating the same A master/slave system architecture including a single wire bus and master device and bus interface coupled to the bus. The system further includes slave devices having respective bus interfaces coupled to the bus. The system further includes a communication protocol... | 02/20/2007 |
| 7167935 | Accessory control interface Disclosed is an interface (10, 40) between a master device (30) and a slave device (20). The interface includes a bit serial bidirectional signal line (10A) for conveying commands and associated data from the master device to the slave de... | 01/23/2007 |
| 7103526 | Method and apparatus for adapting a simulation model to expose a signal internal to the model to a client application A method for exposing the internal signals of a system model or software model of a dynamic system to a client application outside the original modeling environment is provided. A designer of the system model is provided with a way to select internal signals of the ... | 09/05/2006 |
| 7088137 | System, method and program product for extending range of a bidirectional data communication bus A communication system, method and program product are provided for establishing an extended bidirectional communication bus between a first device and a second device. The communication system includes decomposition logic for decomposing a single line, bidirectiona... | 08/08/2006 |
| 7051132 | Bus system and path decision method therefor A bus system and a method of deciding a data transmission path are provided. The bus system includes a plurality of functional blocks; a ring bus which transmits data in a single direction; an arbiter which generates a bus grant signal according to a predetermined a... | 05/23/2006 |
| 6976108 | System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter has programmable rankings for assigning priorities to requests from ... | 12/13/2005 |
| 6928501 | Serial device daisy chaining method and apparatus Methods and apparatus associated with a plurality of serial devices designed to communicate with a bus master in either a daisy chain or a normal configuration are provided. One method includes the step of serially providing a command sequence having a channel ident... | 08/09/2005 |
| 6901487 | Device for processing data by means of a plurality of processors A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor... | 05/31/2005 |
| 6898766 | Simplifying integrated circuits with a common communications bus When integrating a peripheral, it is common practice to use a fully custom design. Custom designs typically optimize performance, size, and energy usage. However, custom designs are more expensive in terms of testing and development time. Rather than designing an in... | 05/24/2005 |
| 6862639 | Computer system including a receiver interface circuit with a scatter pointer queue and related methods A computer system may include a processor, at least one memory coupled to the processor and having a plurality of scattered memory locations each having a pointer associated therewith, and a receiver interface circuit coupled to the at least one memory. The receiver... | 03/01/2005 |
| 6651110 | Configurable object for industrial control and monitoring networks A dedicated memory object for networked, programmable electrical components is designed to be embedded in the components to receive system and component-specific data. The memory object is preferably resident and includes dedicated blocks for system desig... | 11/18/2003 |
| 6502149 | Plural bus data storage system A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a plurality of memory regions and a plurality of control logic sections arranged in a matrix ... | 12/31/2002 |
| 6397281 | Bus arbitration system A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a memory and a plurality of control logic sections interconnected through an arbitration bus.... | 05/28/2002 |
| 6339807 | Multiprocessor system and the bus arbitrating method of the same An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus, determines the priority of utilizing the bus in accordanc... | 01/15/2002 |
| 6286070 | Shared memory access device and method A bus controller for a CCD digital still camera arbitrates competing requests by multiple microcontrollers for a shared memory. One of the microcontrollers is designated to have a higher priority than the other microcontroller(s). In the case of competing... | 09/04/2001 |
| 6185647 | Dynamic bus control apparatus for optimized device connection A priority decision circuit decides priorities of a plurality of slots on the basis of access frequencies or the like. In conformity with these priorities, a bus mapping circuit performs mapping allowing a slot having a higher priority to be connected to ... | 02/06/2001 |
| 6018781 | Work station having simultaneous access to registers contained in two different interfaces A work station which includes a central processing unit (CPU), first and second interface chips connected to respective external or peripheral units, and a local bus connected to the CPU and chips and adapted for multiple byte data communication between t... | 01/25/2000 |
| 5950229 | System for accelerating memory bandwidth A computer system and method process memory requests for access to a computer memory. The computer system arbitrates between current memory requests based on an immediately previous memory request that was most recently selected for transmission to the me... | 09/07/1999 |
| 5931931 | Method for bus arbitration in a multiprocessor system One aspect of the invention relates to a method for arbitrating simultaneous bus requests in a multiprocessor system having a plurality of devices which are coupled to a shared bus. In one version of the invention, the method includes the steps of receivi... | 08/03/1999 |
| 5715475 | Topological identification and initialization of a system for processing video information A method and apparatus for initializing and determining the topological configuration of a system for processing video information is described. The system has a master device and multiple slave devices for transmitting or receiving video information. The... | 02/03/1998 |
| 5210846 | One-wire bus architecture A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude.... | 05/11/1993 |
| 4959775 | Bus regulating system A bus regulating system has a bus shared by a plurality of modules (10, 20, 30) and a bus usage permit signal line (4) in the form of a daisy chain. The usage of the bus is flexibly controlled according to the tasks of the modules (10, 20, 30). Each of th... | 09/25/1990 |
| 4670855 | Interchangeable interface circuit structure The present structure is an interchangeable interface circuit card which per se includes: circuitry which is responsive to being addressed in accordance with its physical location; circuitry to generate signals which identify the circuit being addressed a... | 06/02/1987 |
