Class 710/113 - Centralized bus arbitration

Subclass of Class 710 - Electrical computers and digital data processing systems: input/output
Definition: Subject matter including means or steps for determining
No. of patents: 871
Last issue date: 05/29/2012

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Number	Title	Issue Date
8190802	Circuit, method and arrangement for implementing simple and reliable distributed arbitration on a bus An arbitrator circuit for accessing a bus comprises a logic gate arrangement (406), one input of which is coupled to a first bus line. The circuit comprises a switching arrangement (404, 405, 407). As a response to a control signal the switching arrang...	05/29/2012
8190801	Interconnect logic for a data processing apparatus Interconnect logic is provided for coupling master logic units and slave logic units within a data processing apparatus to enable transactions to be performed. Each transaction comprises an address transfer from a master logic unit to a slave logic unit and one or m...	05/29/2012
8041869	Method and system for bus arbitration A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to c...	10/18/2011
8032678	Shared resource arbitration Masters request access to a shared resource, such as a shared bus. Usage of the shared bus by each of the masters is monitored, a request to use the shared bus by one of the masters is received, and usage of the shared bus by the master is compared with a correspond...	10/04/2011
7908416	Data processing unit and bus arbitration unit An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master is...	03/15/2011
7865645	Bus arbiter, bus device and system for granting successive requests by a master without rearbitration A bus arbiter includes an arbitration stop determining unit and a transaction arbitrating unit. The arbitration stop determining unit generates an arbitration stop signal based upon transaction grouping request signals which indicate whether successive transactions ...	01/04/2011
7861022	Livelock resolution A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution ...	12/28/2010
7827337	Sharing memory interface A device and a method for sharing a memory interface are disclosed. According to preferred embodiments of the present invention, a supplementary control unit included in a digital processor can control some of the pins, constituting a memory interface, to be shared ...	11/02/2010
7779189	Method, system, and computer program product for pipeline arbitration A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is ...	08/17/2010
7769936	Data processing apparatus and method for arbitrating between messages routed over a communication channel A data processing apparatus and method are provided for arbitrating between messages routed over a communication channel. The data processing apparatus has a plurality of processing elements, each processing element executing a process requiring messages to be issue...	08/03/2010
7765349	Apparatus and method for arbitrating heterogeneous agents in on-chip busses A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request delays of the N bus agents and the M bus agents and grants concurrent own...	07/27/2010
7734854	Device, system, and method of handling transactions Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be i...	06/08/2010
7685344	Method of setting priority of devices connected to bus, and apparatus having a plurality of devices and arbiter The remaining time period until the deadline of transfer by a device connected to a bus is measured, the remaining data size to be transferred by the device is detected, and the priority level of the device is set based on the remaining time period and the remaining...	03/23/2010
7668996	Method of piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization An improved method, device and data processing system are presented. In one embodiment, the method includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the b...	02/23/2010
7650451	Arbiter circuit An arbiter circuit includes a priority coefficient calculating unit, a priority coefficient comparator an acceptance determining unit, and a priority determining unit. The priority coefficient calculating unit calculates for each request an arbitration priority coef...	01/19/2010
7620760	Non-high impedence device and method for reducing energy consumption A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit access logics associated with multiple circuits; wherein each circuit ...	11/17/2009
7587542	Device adapted to send information in accordance with a communication protocol A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconne...	09/08/2009
7533206	Resource management device A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given period is set as bus arbitration information for each of the bus mast...	05/12/2009
7500035	Livelock resolution method A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution ...	03/03/2009
7490185	Data processing system, access control method, and access control device A data processing system able to raise the access efficiency to a memory when a plurality of processor access to the memory will be provided. An arbitration program executed by one input/output processing device determines a priority order for the access requests to...	02/10/2009
7464207	Device operating according to a communication protocol A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconne...	12/09/2008
7444447	Arrangement, device and method for controlling bus request signal generation A device, arrangement and method may control bus request timing to disperse bus access timing, so that adverse effects of concentration-on-bus phenomenon may be avoided. The device may include a bus request signal generating circuit may generate a bus request signal...	10/28/2008
7444668	Method and apparatus for determining access permission A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to a plurality of masters (12, 14), determining access permissions (86), providing state information (60...	10/28/2008
7441059	Method and device for data communication A device for data communication between a first host device or a further host device and at least one client device along a shared transmission path includes a first host device, which includes a host application; at least one further host device, which includes a h...	10/21/2008
7437494	Systems and methods for assigning an address to a network device added to an existing network The present invention provides systems, methods, and bus controllers for establishing communication with various network systems located on a network system. Importantly, the systems, methods, and bus controllers of the present invention are capable recognizing that...	10/14/2008
7428607	Apparatus and method for arbitrating heterogeneous agents in on-chip busses A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is det...	09/23/2008
7426709	Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to determine whether a smaller design using arbitration logic at the bu...	09/16/2008
7412556	Method and system for master devices accessing slave devices Techniques for multiple master devices accessing one or more slave devices via a single data bus are disclosed. According to one aspect of the techniques, a bus controller coupled between the master devices and the slave device, wherein the bus controller is configu...	08/12/2008
7412550	Bus system with protocol conversion for arbitrating bus occupation and method thereof A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereb...	08/12/2008
7395360	Programmable chip bus arbitration logic Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bu...	07/01/2008
7386750	Reduced bus turnaround time in a multiprocessor architecture Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus handoff. The method may also include bypassing data from recovery la...	06/10/2008
7373438	System and method for reprioritizing high-latency input/output operations A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/...	05/13/2008
7372768	Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of...	05/13/2008
7370127	High-speed internal bus architecture for an integrated circuit An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interf...	05/06/2008
7370161	Bank arbiter system which grants access based on the count of access requests Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and al...	05/06/2008
7366811	Bus arbitration system A circuit arrangement, program product and method for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices acc...	04/29/2008
7366935	High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described. ...	04/29/2008
7359077	Printing apparatus, control method therefor, and program A CPU monitors the state of a printing apparatus, and controls transmission, to the host, of a control signal for controlling the data reception timing from the host. ...	04/15/2008
7360217	Multi-threaded packet processing engine for stateful packet processing A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to acco...	04/15/2008
7360119	Method and apparatus for handling SAS/SATA communication deadlock Broadly speaking, a method and apparatus is provided for identifying and responding to a deadlock condition in a SAS/SATA communication process. More specifically, an initiator device involved in the SAS/SATA communication process is defined to recognize a received ...	04/15/2008

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Class 710/113 - Centralized bus arbitration