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| Number | Title | Issue Date |
| 8145815 | Data processing system In a hierarchical bus structure employing a fixed-priority bus access arbitration scheme, accurate arbitration of bus access requests can be carried out even in situations where priority levels are updated according to a system operation mode. In each of a plurality... | 03/27/2012 |
| 8046513 | Out-of-order executive bus system and operating method thereof An operating method applied to an out-of-order executive bus system includes: according to dependency constraints, linking requests using the bus system to form dependency request links having an order; and processing the order of the requests according to the depen... | 10/25/2011 |
| 8006013 | Method and apparatus for preventing bus livelock due to excessive MMIO The disclosure relates to a method and apparatus to efficiently address livelock in a multi-processor system. In one embodiment, the disclosure is directed to a method for preventing a system bus livelock in a system having a plurality of processors communicating re... | 08/23/2011 |
| 7970970 | Non-blocking address switch with shallow per agent queues In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store... | 06/28/2011 |
| 7945719 | Controller link for manageability engine An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source t... | 05/17/2011 |
| 7779188 | System and method to reduce memory latency in microprocessor systems connected with a bus A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message when it cannot supply the requested data in a short period of time. Wh... | 08/17/2010 |
| 7752366 | Non-blocking address switch with shallow per agent queues In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store... | 07/06/2010 |
| 7590784 | Detecting and resolving locks in a memory unit In one embodiment, the present invention includes an apparatus having a first counter to count dispatches of a senior request in a memory unit, a second counter to count cycles of a processor coupled to the memory unit, and a controller coupled to the first and seco... | 09/15/2009 |
| 7526590 | Systems and methods for remote pipe resource management in wireless adapters Embodiments include systems and methods for management of RPIPES in a Wireless Universal Serial Bus (WUSB) environment comprising at least one WUSB device. RPIPE management computer code is executed to perform RPIPE management functions including monitoring RPIPE me... | 04/28/2009 |
| 7519755 | Combined command and response on-chip data interface for a computer system chipset An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit is... | 04/14/2009 |
| 7490184 | Systems and methods for data intervention for out-of-order castouts Systems and methods for data intervention for out-of-order castouts are disclosed. Embodiments provide for transmitting snoopable requests received from one or more requesting devices to one or more snoopable devices, which may include requesting devices. Each snoop... | 02/10/2009 |
| 7480754 | Assignment of queue execution modes using tag values The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment a tag is assigned for each of several disc access commands sent by the host. Two or more queues are created, each having a queue execution mode. Wh... | 01/20/2009 |
| 7461190 | Non-blocking address switch with shallow per agent queues In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store... | 12/02/2008 |
| 7424562 | Intelligent PCI bridging consisting of prefetching data based upon descriptor data A bridging device has at least two ports. The first port allows the device to communicate with devices on an expansion bus and at least one other port to allow the bridge to communicate with a system memory on a system bus or other devices on another expansion bus. ... | 09/09/2008 |
| 7421545 | Method and apparatus for multiple sequence access to single entry queue Bus address, function and system information in relation to bus requests are maintained in a centralized location (702). Parallel access to the centralized data is facilitated through the use of pointers to the centralized location. Bus transaction operations... | 09/02/2008 |
| 7406554 | Queue circuit and method for memory arbitration employing same A memory access arbitration scheme is provided where transactions to a shared memory are stored in an arbitration queue. A collapsible queuing structure and method are provided, such that once a transaction is serviced, higher order entries ripple down in the queue ... | 07/29/2008 |
| 7401126 | Transaction switch and network interface adapter incorporating same A transaction switch and integrated circuit incorporating said for switching data through a shared memory between a plurality of data interfaces that support different data protocols, namely packetized interfaces like InfiniBand and addressed data interfaces like PC... | 07/15/2008 |
| 7386681 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/r... | 06/10/2008 |
| 7386750 | Reduced bus turnaround time in a multiprocessor architecture Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus handoff. The method may also include bypassing data from recovery la... | 06/10/2008 |
| 7386682 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is disp... | 06/10/2008 |
| 7373445 | Method and apparatus for allocating bus access rights in multimaster bus systems A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least ... | 05/13/2008 |
| 7373444 | Systems and methods for manipulating entries in a command buffer using tag information Systems and methods for facilitating the location of entries in a buffer where a slave device stores information related to an active transaction so that the entries can be removed if the corresponding transactions are canceled. In one embodiment, multiple master de... | 05/13/2008 |
| 7373462 | Snoop filter for filtering snoop requests A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises provid... | 05/13/2008 |
| RE40317 | System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the ... | 05/13/2008 |
| 7370133 | Storage controller and methods for using the same In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later ... | 05/06/2008 |
| 7360009 | Data transfer apparatus for limiting read data by a bus bridge with relay information A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, ... | 04/15/2008 |
| 7356737 | System, method and storage medium for testing a memory module A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnec... | 04/08/2008 |
| 7353317 | Method and apparatus for implementing heterogeneous interconnects Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transf... | 04/01/2008 |
| 7353308 | Avoiding oscillation in self-synchronous bi-directional communication system In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to... | 04/01/2008 |
| 7340568 | Reducing number of rejected snoop requests by extending time to respond to snoop request A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit.... | 03/04/2008 |
| 7331010 | System, method and storage medium for providing fault detection and correction in a memory subsystem A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the... | 02/12/2008 |
| 7328300 | Method and system for keeping two independent busses coherent Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and th... | 02/05/2008 |
| 7315912 | Deadlock avoidance in a bus fabric Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted ... | 01/01/2008 |
| 7310649 | Data structure for efficient enqueuing and dequeuing A data structure for efficient enqueuing and dequeuing is disclosed. The structure includes a horizontally linked list, an array, a vertically linked list, and a head pointer. Entity ranks are distributed over the array, where each array entry has a range of ranks. ... | 12/18/2007 |
| 7308510 | Method and apparatus for avoiding live-lock in a multinode system A reordering priority to grant higher priority for a request over a response when a predetermined condition is detected for live-lock prevention is discussed. Specifically. A a circuit and flowchart for preventing a live lock situation is discussed without a need fo... | 12/11/2007 |
| 7305574 | System, method and storage medium for bus calibration in a memory subsystem A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memor... | 12/04/2007 |
| 7302684 | Systems and methods for managing a run queue Various implementations of the described subject associate a plurality of threads that are sorted based on thread priority with a run queue in a deterministic amount of time. The run queue includes a first plurality of threads, which are sorted based on thread prior... | 11/27/2007 |
| 7290065 | Method, system and product for serializing hardware reset requests in a software communication request queue A system, method, and product are disclosed in a data processing system for serializing hardware reset requests in a software communication request queue in a processor card. The processor card processes software communication requests utilizing the queue in a seria... | 10/30/2007 |
| 7287087 | Communications network for dynamic reprioritization A communications network comprising at least one source unit is configured to generate messages for relay to a portal node through at least one smart node. The smart node includes a dynamic reprioritization controller capable of dynamically reprioritizing the relaye... | 10/23/2007 |
| 7281055 | Routing mechanisms in systems having multiple multi-processor clusters A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exce... | 10/09/2007 |
