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Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 8151025 | Fast round robin circuit The fast round robin circuit includes AND gates, OR gates, multiplexers and four D flip-flop gates configured to handle requests using linear propagation of a single grant token. In this manner the device avoids wasting clock cycles when some of the arbitrated entit... | 04/03/2012 |
| 8032677 | Selection circuit and packet processing apparatus An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A firs... | 10/04/2011 |
| 7779187 | Data communication circuit and arbitration method A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to a weight-information updating unit in real time, and is reflected in ... | 08/17/2010 |
| 7739436 | Method and apparatus for round robin resource arbitration with a fast request to grant response Various methods and apparatuses are described for an arbitration unit that implements a round robin policy. Each requesting device has an equal chance of accessing a shared resource based upon a current request priority assigned to that requesting device. The arbitr... | 06/15/2010 |
| 7631130 | Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor A circuit for selecting one of N requestors in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicati... | 12/08/2009 |
| 7512729 | Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plur... | 03/31/2009 |
| 7509447 | Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor An apparatus for selecting one of N requestors of a shared resource in a round-robin fashion is disclosed. One or more of the N requestors may be disabled from being selected in a selection cycle. The apparatus includes a first input that receives a first value spec... | 03/24/2009 |
| 7451258 | Rotating priority queue manager The present invention is a rotating priority queue manager. A rotating priority queue manager in accordance with the present invention may include a plurality of source data channels, a corresponding plurality of processing resources, and an arbitrating interface di... | 11/11/2008 |
| 7428607 | Apparatus and method for arbitrating heterogeneous agents in on-chip busses A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is det... | 09/23/2008 |
| 7385965 | Multiprocessor control block for use in a communication switch and method therefore A communication switch that includes a multiprocessor control block and a method therefore is presented. The multiprocessor control block includes a centralized resource and routing processor that controls resource allocation and routing functionality within the swi... | 06/10/2008 |
| 7373445 | Method and apparatus for allocating bus access rights in multimaster bus systems A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least ... | 05/13/2008 |
| 7366810 | Method and system for multi-processor arbitration A computing system includes one or more buses, a plurality of bus agents, and a chip set. The plurality of bus agents are capable of accessing at least one of the buses. The chipset arbitrates access to a bus for at least two of the bus agents such that utilization ... | 04/29/2008 |
| 7350003 | Method, system, and apparatus for an adaptive weighted arbiter An adaptive weighted arbitration algorithm that is user configurable is discussed. The arbitration logic and algorithm considers past arbitration history events and is dynamic to allow for losing bidders to increase their probability of being selected to access the ... | 03/25/2008 |
| 7350002 | Round-robin bus protocol A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the dev... | 03/25/2008 |
| 7343436 | Synchronous electronic control system and system control method The present invention is carried out to provide a system controller, a control system and a system control method which are inexpensive, highly stable, capable of storing all information and past record at a time when one of the devices is down and capable of switch... | 03/11/2008 |
| 7337251 | Information processing device with priority-based bus arbitration The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has storage units retaining information representing priorities of the access r... | 02/26/2008 |
| 7328292 | Arbitration method and device In an arbitration device, the entire transfer efficiency is improved without increasing the operating frequency and the number of pins. An overflow monitor mechanism generates an alarm once detecting a danger of occurrence of an overflow in an internal buffer group.... | 02/05/2008 |
| 7324537 | Switching device with asymmetric port speeds In general, in one aspect, the disclosure describes a switching device that includes a plurality of ports. The ports operate at asymmetric speeds. The apparatus also includes a switching matrix to provide selective connectivity between the ports. The apparatus furth... | 01/29/2008 |
| 7325082 | System and method for guaranteeing transactional fairness among multiple requesters A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is used to control servicing of multiple requests made by multiple request... | 01/29/2008 |
| 7315909 | Hierarchized arbitration method An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates i... | 01/01/2008 |
| 7305507 | Multi-stage round robin arbitration system Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is configured to partition a plurality of requests into a plurality of bloc... | 12/04/2007 |
| 7302510 | Fair hierarchical arbiter A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request... | 11/27/2007 |
| 7296105 | Method and apparatus for configuring an interconnect to implement arbitration Various methods and apparatuses are described in which an interconnect couples to a plurality of initiator network resources and a plurality of target network resources. The interconnect may include a first stage of circuitry, a second stage of circuitry, and an arb... | 11/13/2007 |
| 7284080 | Memory bus assignment for functional devices in an audio/video signal processing system The invention provides a system and method for memory bus assignment for a plurality of functional devices. According to a preferred embodiment, the invention provides a system comprising a plurality of functional devices accessing a memory bus wherein the memory bu... | 10/16/2007 |
| 7281071 | Method for designing an initiator in an integrated circuit A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed routing network. The initiator port is implemented by configuring wh... | 10/09/2007 |
| 7266626 | Method and apparatus for connecting an additional processor to a bus with symmetric arbitration A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An additional agent may monitor the symmetric arbitration of the symmetri... | 09/04/2007 |
| 7260688 | Method and apparatus for controlling access to memory circuitry Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing system. A plurality of ports is respectively coupled to said plurality... | 08/21/2007 |
| 7260609 | Method and communication system for data exchanging data between users of a bus system The present invention provides a method and a communications system for the exchange of data between at least two users who are in contact with one another using a bus system. The data are included in messages which are transmitted by users over the bus system. A sp... | 08/21/2007 |
| 7254661 | Methods, circuits, and computer program products for variable bus arbitration Arbitration for a communications channel can be provided by scheduling a grant for future access to one of a plurality of requestors to a communications channel shared by the plurality of requestors based on an indication of which of the plurality of requestors is g... | 08/07/2007 |
| 7254674 | Distribution of I/O requests across multiple disk units A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical... | 08/07/2007 |
| 7249210 | Bus access arbitration scheme A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight... | 07/24/2007 |
| 7243168 | Low power CD-ROM player with CD-ROM subsystem for portable computer capable of isolating digital computer bus from CD-ROM drive A computer subsystem of a computer includes a CPU, RAM, display, storage device, input device(s), and a digital-audio generating IC. A CD-ROM subsystem of the computer includes a CD-ROM drive and CD-ROM control buttons for controlling CD-ROM drivers operation while ... | 07/10/2007 |
| 7240135 | Method of balancing work load with prioritized tasks across a multitude of communication ports A processor is used to evaluate information regarding the number, size, and priority level of data transfer requests sent to a plurality of communication ports. Additional information regarding the number, size, and priority level of data requests received by the co... | 07/03/2007 |
| 7236499 | Resource arbitration in accordance with a masked request vector According to some embodiments, a resource is allocated in accordance with a masked request vector. For example, a masking unit may receive a request vector and provide a masked request vector, wherein each bit in the request vector represents a requestor and indicat... | 06/26/2007 |
| 7231479 | Round robin selection logic improves area efficiency and circuit speed A method and apparatus are provided for efficiently operating a round robin arbitration system in a given computer system. The system utilizes a series of banks of requestors and pointer. The banks of requestors and pointers operate on sequential AND-OR-Inverter/OR-... | 06/12/2007 |
| 7225280 | Portable device for one-on-one transfer between another such device wherein device is restricted to data storage and transfer with single interface for data exchange A device, a method and a system for portable data storage and transfer through a simplified device interface. The operations of the device are restricted, in order to increase the ease of use of the device, and in order to provide certain core functions. These core ... | 05/29/2007 |
| 7209992 | Graphics display system with unified memory architecture A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that ... | 04/24/2007 |
| 7200699 | Scalable, two-stage round robin arbiter with re-circulation and bounded latency A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality ... | 04/03/2007 |
| 7197577 | Autonomic input/output scheduler selector The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped against a corresponding desired set of heuristics. Heuristics relating to ... | 03/27/2007 |
| 7194567 | Method and system for ordering requests at a bus interface A bus bridge for coupling between a first bus and a second bus includes: multiple ticket registers; a ticket dispenser counter; and a ticket call counter. The ticket dispenser counter dispenses a ticket value to a request received at the bridge from the first bus fo... | 03/20/2007 |
