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| Number | Title | Issue Date |
| 8180940 | Method and system for transmission of cyclic and acyclic data over a transmission channel that takes into account real-time capability A method is disclosed for the transmission of cyclic and acyclic data by means of a transmission channel between at least two user devices connected to the transmission channel, with a protocol-specific cyclic data transmission being carried out at least between one... | 05/15/2012 |
| 8161216 | Interface transmission device and method An interface transmission device and method are disclosed. The interface device, located in a first device, includes a transmission interface and a receiving circuit. The transmission interface receives an initialization signal and an interface signal. The receiving... | 04/17/2012 |
| 8161217 | Method and system for a RFIC master Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-c... | 04/17/2012 |
| 8156272 | Multiple communication channels on MMC or SD CMD line The claimed subject matter can provide an architecture that interfaces a single slave device such as a UICC smartcard with multiple host controllers. For example, a secondary host can be interfaced between a primary host (e.g. a controller in a cellular phone, a PDA... | 04/10/2012 |
| 8156274 | Direct slave-to-slave data transfer on a master-slave bus A method and system for transferring data between two slave devices. A system includes a master device and first and second slave devices coupled to the master device by a peripheral bus. The master device is configured to configure the first slave device as a sourc... | 04/10/2012 |
| 8156273 | Method and system for controlling transmission and execution of commands in an integrated circuit device A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined ba... | 04/10/2012 |
| 8131900 | Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device w... | 03/06/2012 |
| 8122173 | Serial peripheral interface (SPI) circuit having driving circuit with data input and output common pin and display using the same A serial peripheral interface (SPI) circuit and a display using the same are provided. The SPI circuit includes a mater device and a slave device. A serial data input pin and a serial data output pin of the slave device are both electrically connected to a data inpu... | 02/21/2012 |
| 8117366 | Method and device for detecting locations of bus subscribers In order to register the order of bus subscribers (12) when starting a system without the use of a token line to be specifically laid for his purpose along the two-wire bus (11), the bus master (13) temporarily activates a reflective discontinui... | 02/14/2012 |
| 8103814 | Electronic apparatus and data sending/receiving method thereof An electronic apparatus to allow data to be sent and received between a master unit and a slave unit through a peripheral component interconnect (PCI) bus is provided. Each of the master unit and the slave unit comprises a data interface having a plurality of pins t... | 01/24/2012 |
| 8095714 | Electronic device capable of automatically switching between a master mode and a slave mode An electronic device, includes a USB interface, a processing unit, a master-slave select triggering circuit, a controlling unit, a selection circuit and a switching circuit. The master-slave selection triggering circuit including an input port, a first output port a... | 01/10/2012 |
| 8082378 | Master and slave side arbitrators associated with programmable chip system components Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on... | 12/20/2011 |
| 8082377 | Data transmission and reception system, master device, and slave device A master device for performing data transmission and reception with a slave device includes: a data transmission and reception circuit for performing transmission of data to the slave device and reception of data from the slave device via a first transmission path i... | 12/20/2011 |
| 8055826 | Communication system and method for operation thereof A communication system comprises a multiplicity of slave units and a master unit. The slave units are coupled to one another via a first communication path and a second communication path, the first communication path and the second communication path operating in o... | 11/08/2011 |
| 8046512 | Communication system with master and slave exchanging control data in predetermined communication period A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication p... | 10/25/2011 |
| 8041867 | Method and apparatus for enhancing data rate of advanced micro-controller bus architecture A method for enhancing data rate of an advanced micro-controller bus architecture (AMBA) having an AHB system and an APB system includes simultaneously receiving control signals outputted from a plurality of master devices of the AHB system, and controlling a plural... | 10/18/2011 |
| 8041868 | Bus relay device and bus control system including bus masters, interconnect section, and bridge section A combination includes a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus, a second bus master coupled to the first bus to output a second signal group including at least one of signals onto ... | 10/18/2011 |
| 8028112 | I/O device, network system with I/O device and communication method in network system with I/O device An I/O device is provided to accurately synchronize clocks between nodes to have a device driving signal directly made out from the clocks, so that operation timing can be synchronized between the nodes regardless of a processing flicker on a host computer and a del... | 09/27/2011 |
| 8015336 | Method of compensating for propagation delay of tri-state bidirectional bus in a semiconductor device A semiconductor device for detecting and compensating for a propagation delay of a tri-state bidirectional bus connected between a master block and a plurality of slave blocks. The master block controls the slave blocks. A bidirectional bus connects the master block... | 09/06/2011 |
| 8010724 | 12C/SMBus ladders and ladder enabled ICs I2C/SMBus ladders and ladder enabled ICs (devices) to enable daisy-chained I2C/SMBus communication. The devices are particularly useful in monitoring and/or servicing high-voltage battery stacks and other voltage stacks. The devices are powered from a respective vol... | 08/30/2011 |
| 8006012 | Data storage system A data storage system is provided. The data storage system includes a first storage module for storing a first data, a second storage module for storing a second data, a control module and a processing module. The control module generates a first control signal and ... | 08/23/2011 |
| 8001306 | Interface unit and communication system having a master/slave structure An interface unit is provided for a communication system comprising a master unit and a plurality of slave units serially connecting the master unit via a double ring structure comprising a first communication path and a second communication path. The interface unit... | 08/16/2011 |
| 7984217 | Data transmission method, serial bus system, and switch-on unit for a passive station In a serial bus system data in the form of telegrams, representing process images of control tasks of the active station, are transmitted to the connected passive stations, and the process data are allocated to the process images in the passive station. ... | 07/19/2011 |
| 7984215 | Semiconductor device The router which relays a transfer request and a reply between master and slave components has request-control circuits provided therein. The request-control circuits judge the slave component to transfer a request from each master component to, and arbitrate the co... | 07/19/2011 |
| 7984216 | Method and system for a RFIC master Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-c... | 07/19/2011 |
| 7966438 | Two-wire communications bus system A low-cost, two-wire, half-duplex high speed powered communications bus having a master/controller and one or more slave/sensor/interface units. The master/controller may have a current-limited power supply, and receive/transmit circuitry. Each slave/sensor/interfac... | 06/21/2011 |
| 7937514 | CWUSB host management system Universal Serial Bus (USB) is a Master/Salve or Host/Device system in which there is only one host and one or more devices connected by cables to the host. To connect a USB device to a different host controller (say another PC), the user unplugs the USB cable and es... | 05/03/2011 |
| 7934034 | Simultaneous control of multiple I/O banks in an I2C slave device Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device regi... | 04/26/2011 |
| 7921249 | Weakly ordered processing systems and methods The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barri... | 04/05/2011 |
| 7917676 | Efficient execution of memory barrier bus commands with order constrained memory accesses The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barri... | 03/29/2011 |
| 7913012 | System and method for connecting a master device with multiple groupings of slave devices via a LINBUS network A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is located within the microcontroller unit for digitally communicating with ... | 03/22/2011 |
| 7913013 | Semiconductor integrated circuit A semiconductor integrated circuit according to an aspect of the invention includes a plurality of master devices which issue data transfer requests, at least one slave device which performs data transfer in accordance with the data transfer requests, and a network ... | 03/22/2011 |
| 7904625 | Power savings for universal serial bus devices An apparatus includes a Universal Serial Bus (USB) transceiver of a USB host controller, a first pull-down resistor, a first switch, a second pull-down resistor, a second switch, and a detachment module. The USB transceiver has a differential output. The first switc... | 03/08/2011 |
| 7895381 | Data accessing system A data accessing system bridges a first master device and a second master device to a first slave device and a second slave device. The data accessing system includes a register, a first multiplexer, a second multiplexer and a control unit. The amount of data that t... | 02/22/2011 |
| 7890684 | Two-cycle return path clocking Return path clocking mechanism for a system including a master device connected to a plurality of slave devices via a bus. The master device may first generate a global clock. The master device may transmit data to one or more of the slave devices at a rate of one b... | 02/15/2011 |
| 7886098 | Memory access security management A data processing apparatus and method for generating access requests is provided. A bus master is provided which can operate either in a secure domain or a non-secure domain of the data processing apparatus, according to a signal received from external to the bus m... | 02/08/2011 |
| 7886097 | Bus arbitration system, medium, and method A bus arbitration system, medium, and method. The bus arbitration system can arbitrate access to a bus for a plurality of masters, requesting the use of a bus to which at least one slave is connected, and may include a bus use granting unit that outputs a plurality ... | 02/08/2011 |
| 7882290 | Method for preventing transaction collision on bus and computer system utilizing the same A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on... | 02/01/2011 |
| 7882289 | Slave apparatus in a data transmission system, data transmission system and data transmission method in a data transmission system In a data transmission system having a plurality of apparatuses connected to one another in a cascade, each slave apparatus has an identification number retention section retaining the same identification number as the other slave apparatuses, a receiver receiving d... | 02/01/2011 |
| 7877533 | Bus system, bus slave and bus control method A bus system includes one or more bus masters, one or more bus slaves, and a response unit. When an access request to a resource of a bus slave is sent from a bus master, the response unit outputs a wait response that is either a blocking wait response to cause the ... | 01/25/2011 |
