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| Number | Title | Issue Date |
| 7904499 | Methods and apparatus for carry generation in a binary look ahead system Methods and apparatus provide for a carry generation tree for a carry look-ahead binary adder, which includes N stages of operators, reducers, and/or repeaters, wherein: a first of the stages receives binary outputs from a series of binary adders; a last of the stag... | 03/08/2011 |
| 7194501 | Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folde... | 03/20/2007 |
| 7191205 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 03/13/2007 |
| 7185043 | Adder including generate and propagate bits corresponding to multiple columns An apparatus for adding a first value and a second value each including a plurality of bits includes combiner units, a carry creation unit and summation units. Bits corresponding to bit positions of the first and the second value form respective columns. Each of the... | 02/27/2007 |
| 7062499 | Enhanced multiway radix tree and related methods A method and apparatus for assigning a logical level number to a symbol in a key comprising a string of symbols, and storing an entry for the key in a level of nodes in a multiway radix tree based at least in part on the logical level number instead of on a path bet... | 06/13/2006 |
| 7007059 | Fast pipelined adder/subtractor using increment/decrement function with reduced register utilization A fast pipelined adder/subtractor using increment/decrement functions with reduced register utilization. Embodiments of the present invention replace double width registers with incrementor elements, pipelined single width registers, and pipelined carry bits. This i... | 02/28/2006 |
| 6782406 | Fast CMOS adder with null-carry look-ahead A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry si... | 08/24/2004 |
| 6438572 | Adder having reduced number of internal layers and method of operation thereof An adder, a processor (such as a microprocessor or digital signal processor), and methods of adding in such adder or processor. In one embodiment, the adder includes: (1) a first and second units in a first logic layer, the first unit receiving first and ... | 08/20/2002 |
| 6199090 | Double incrementing, low overhead, adder A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight ("first weight"). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receiv... | 03/06/2001 |
| 5944777 | Method and apparatus for generating carries in an adder circuit An adder circuit to generate carry-outs and a method implemented by the adder circuit. First and second groups of consecutive group generate terms are calculated. The first group of group generate terms are combined to calculate a first result at a first ... | 08/31/1999 |
| 5943251 | Adder which handles multiple data with different data types An adder circuit includes various methods to control the carry bit at data boundaries when attempting to process multiple data of multiple types. One method is to generate both propagate and generate signals from the input data and modified propagate and ... | 08/24/1999 |
| 5847984 | Combination propagate and generate carry lookahead gate Carry lookahead adders reduce the number of logic levels required to sum two numbers. A pure carry lookahead adder, however, requires circuits with large fan-outs and fan-ins making it impractical to build for a large number of bits. Carry lookahead tree ... | 12/08/1998 |
| 5508952 | Carry-lookahead/carry-select binary adder A carry-lookahead/carry-select binary adder includes a plurality of Manchester carry-lookahead cells arranged by length in monotonically increasing order at a first level and a carry-lookahead cell(s) at a second level connected to the first level cells. ... | 04/16/1996 |
| 5479356 | Computer-aided method of designing a carry-lookahead adder Using a computer-aided method to design carry-lookahead adders to add two binary numbers and an input carry bit. In the first preferred embodiment, a length-number and a blocks-in-group number are entered into the computer by a user. The computer, respond... | 12/26/1995 |
| 5434810 | Binary operator using block select look ahead system which serves as parallel adder/subtracter able to greatly reduce the number of elements of circuit with out sacrifice to high speed of computation A binary operator comprises a plurality of carry select adder circuits each including a cumulative carry propagate signal generating means and a cumulative carry generate signal generating means and/or a plurality of block look ahead carry generator circu... | 07/18/1995 |
| 5289392 | Adder This invention has an object to provide a device possible to add analog values. The adder of this invention input an output of an operational amplifier to a reference voltage terminal on the output side of another operational amplifier, adds analog values... | 02/22/1994 |
| 5276635 | Method and apparatus for performing carry look-ahead addition in a data processor A carry look-ahead (CLA) adder accommodates a late carry-in from a low-order external 32-bit adder to enable a 96-bit addition to be performed in the same time in which the CLA adder (60) performs a 64-bit addition. Within each adder slice, intermediate g... | 01/04/1994 |
| 5251164 | Low-power area-efficient absolute value arithmetic unit A high-speed, area efficient, low-power absolute value arithmetic unit that efficiently produces the absolute value of the difference of two input operands. This arithmetic unit is adaptable to provide other output functions. Further, the arithmetic unit ... | 10/05/1993 |
| 5235539 | Method and apparatus for generating carry out signals A circuit for determining the carry out from the addition of two numbers independent of the determination of the sum of the two numbers including apparatus for determining a first carry out from each bit position for a carry in of a first value, apparatus... | 08/10/1993 |
| 5166899 | Lookahead adder In a lookahead adder of the type wherein carry signals for successive stages of the adder are derived by a pyramid of hierarchically-arranged logic circuits, supplemented by carry signals from intermediate ones of the adder stages. The need to rely on suc... | 11/24/1992 |
| 5095458 | Radix 4 carry lookahead tree and redundant cell therefor A high radix carry lookahead tree includes a plurality of tree nodes, each of the tree nodes including a carrying chain or a variation thereof, and/or a NAND gate chain or a variation thereof; and each tree node may have three or more children.... | 03/10/1992 |
| 5043934 | Lookahead adder with universal logic gates A lookahead adder with identical logic gates in all but the first of its lookahead sections. All such identical gates implement the logic function M=X+Y.Z.... | 08/27/1991 |
| 4858168 | Carry look-ahead technique having a reduced number of logic levels A 32-bit adder utilizes an optimal partitioning scheme for improving the 32-bit carry look-ahead. Instead of relying on the powers-of-four partitioning scheme used in prior art adders, the inventive technique uses "double generate" and "double propagate" ... | 08/15/1989 |
| 4163211 | Tree-type combinatorial logic circuit A tree-type combinatorial logic circuit comprising a plurality of identical functional units which may be arranged to operate as an N-bit magnitude comparator, a carry generator for an N-bit adder, or a parity predictor for 2N-bit binary counter. Each of ... | 07/31/1979 |
