Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 8126955 | N bit adder and the corresponding adding method An n bit adder includes first computing circuit with 2n inputs for receiving n values of bits of first and second binary numbers and an additional input for receiving an input carry digit. The first computing circuit elaborates from each of the n pairs of bit values... | 02/28/2012 |
| 7424508 | Self-timed carry look-ahead adder and summation method thereof A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a M... | 09/09/2008 |
| 7325025 | Look-ahead carry adder circuit A look-ahead carry adder circuit has multiple stages that are grouped into a carry generation blocks. The size of one of the carry generation blocks is three stages. There may be other carry generation blocks that are of a size that is a whole number multiple of thr... | 01/29/2008 |
| 7299355 | Fast SHA1 implementation Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which SHA1 multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. As described in this ... | 11/20/2007 |
| 7289455 | Network statistics In general, in one aspect, a method is provided for of tracking a network statistic stored within a collection of bits. The method includes storing the collection of bits storing the network statistic as at least a first portion and a second portion. The first porti... | 10/30/2007 |
| 7277909 | High speed adder Provided is an adder composed of (N+1) circuit stages in the ease of 2.sup.N bits. In the case of N=4 (that is, 16 bits), provisional carries that indicate the case where carry is produced from a low order bit and the case where no carry is produced therefrom are ge... | 10/02/2007 |
| 7260595 | Logic circuit and method for carry and sum generation and method of designing such a logic circuit Logic circuit for generating carry or sum bit output by combining binary inputs, includes bit level carry generate and propagate function logic receiving binary inputs and generating bit level carry generate/propagate function bits for binary inputs by respectively ... | 08/21/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7206802 | Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry... | 04/17/2007 |
| 7139789 | Adder increment circuit In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating wheth... | 11/21/2006 |
| 7136888 | Parallel counter and a logic circuit for performing multiplication A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of co... | 11/14/2006 |
| 7111034 | Carry foreknowledge adder A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a un... | 09/19/2006 |
| 7085796 | Dynamic adder with reduced logic A dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added. The method for implementing the incentive adder users a novel X... | 08/01/2006 |
| 7085798 | Sense-amp based adder with source follower pass gate evaluation tree A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amp... | 08/01/2006 |
| 7042246 | Logic circuits for performing threshold functions Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic... | 05/09/2006 |
| 7028069 | Dynamic circuit using exclusive states The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of ... | 04/11/2006 |
| 7016932 | Adders and adder bit blocks having an internal propagation characteristic independent of a carry input to the bit block and methods for using the same Bit blocks for an adder are provided which include a first bit stage that generates a first bit associated propagation characteristic (bapc). The bapc is independent of a carry input to the bit block from another bit block of the adder. Additional bit stages may be ... | 03/21/2006 |
| 7003545 | High performance carry chain with reduced macrocell logic and fast carry lookahead A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B... | 02/21/2006 |
| 6990510 | Wide adder with critical path of three gates Apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit. In one embodiment, the apparatus comprises a plurality of gates, the critical path through the plurality of gates being three gates delays for some embodiment... | 01/24/2006 |
| 6970899 | Calculating unit and method for subtracting Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing through the adder block. Depending on the carry pass output signal, a ... | 11/29/2005 |
| 6965910 | Calculating unit and method for adding A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder block, which determines whether a carry passes fully through the respective adder block. If it is determined t... | 11/15/2005 |
| 6957245 | Ultra-fast adder A carry look-ahead adder capable of adding or subtracting two input signals includes first stage logic having a plurality of carry-create and carry-transmit logic circuits each coupled to receive one or more bits of each input signal. Each carry-create circuit gener... | 10/18/2005 |
| 6918024 | Address generating circuit and selection judging circuit An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the... | 07/12/2005 |
| 6912560 | Adder with improved overflow flag generation An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at lea... | 06/28/2005 |
| 6909767 | Logic circuit Circuit for selecting a second set of binary inputs according to the number of high input signals applied to a first input set. A first subcircuit has the first input set, logic generating control output signals, each control output signal represents whether the fir... | 06/21/2005 |
| 6742014 | Conditional carry encoding for carry select adder The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only o... | 05/25/2004 |
| 6205463 | Fast 2-input 32-bit domino adder In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section... | 03/20/2001 |
| 6175852 | High-speed binary adder A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple eight-bit group generate circuits... | 01/16/2001 |
| 5943251 | Adder which handles multiple data with different data types An adder circuit includes various methods to control the carry bit at data boundaries when attempting to process multiple data of multiple types. One method is to generate both propagate and generate signals from the input data and modified propagate and ... | 08/24/1999 |
| 5920498 | Compression circuit of an adder circuit An adder circuit includes a 4-2 compression circuit in which a NAND signal of a first input signal and a second input signal and an exclusive-OR signal of the first and second signals are produced. When the exclusive-OR output is true, a third signal is o... | 07/06/1999 |
| 5912833 | Carry increment adder using clock phase A carry increment adder (CIA) using a clock phase in which the CIA performs at an increased speed but uses a much smaller chip area than a general fast adder structure. In the CIA from 1 to N partial adder modules (RCA) which generate partial sum and part... | 06/15/1999 |
| 5896308 | Combinational logic circuit The present invention relates to a combinational logic circuit including at least a pair of inputs and an output line; at least a first module and a symmetrical module; the first module including a parallel cell and a series cell; the parallel cell includ... | 04/20/1999 |
| 5636156 | Adder with improved carry lookahead structure An adder circuit is disclosed having an improved carry lookahead arrangement. The number of carry lookahead stages required is log n, where n is equal to the number of bits in the adder. This arrangement has fanout limit based on the number of sets of pro... | 06/03/1997 |
| 5555517 | Apparatus and method for efficient carry skip incrementation A carry-skip incrementor mitigating propagation delay experienced by conventional ripple carry incrementors without employing a substantially greater device count, includes a plurality of circuit blocks operating in combination with a plurality of logic g... | 09/10/1996 |
| 5508952 | Carry-lookahead/carry-select binary adder A carry-lookahead/carry-select binary adder includes a plurality of Manchester carry-lookahead cells arranged by length in monotonically increasing order at a first level and a carry-lookahead cell(s) at a second level connected to the first level cells. ... | 04/16/1996 |
| 5500813 | Circuit for adding multiple-bit binary numbers An adder includes carry generation & propagation circuits, a carry evaluation circuit and a final sum circuit, wherein the carry generation & propagation circuit and the sum circuit are composed of transmission gates, and the operation can be carried out ... | 03/19/1996 |
| 5487025 | Carry chain adder using regenerative push-pull differential logic A carry indicating circuit selectively generates a carry-in signal indicating whether the addition of a first plurality of bits results in a carry. A first carry chain circuit selectively generates a first carry-out signal indicating whether the addition ... | 01/23/1996 |
| 5394352 | Carry lookahead circuit for semiconductor integrated circuit A carry lookahead circuit for an operation circuit having arithmetic units includes an AND gate and an OR gate for each arithmetic unit. A lookahead carry signal to be inputted to a third arithmetic unit of the operation circuit is the output of the OR ga... | 02/28/1995 |
| 5386377 | Parallelized borrow look ahead subtractor Therefore, according to the present invention, borrow look ahead circuitry suitable for use in a FIFO memory allows the difference between two values to be quickly generated and this difference compared to a third value. A borrow look ahead element genera... | 01/31/1995 |
| 5375081 | High speed adder using a varied carry scheme and related method A high-speed adder using a varied carry scheme, such as one of the carry-lookahead (CLA) type (30), includes a plurality of adder groups (32-37) each receiving some bits of two input operands. The adder groups are not identical but instead each adder grou... | 12/20/1994 |
