Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7358761 | Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from confi... | 04/15/2008 |
| 7349938 | Arithmetic circuit with balanced logic levels for low-power operation An adder circuit includes a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals app... | 03/25/2008 |
| 7325025 | Look-ahead carry adder circuit A look-ahead carry adder circuit has multiple stages that are grouped into a carry generation blocks. The size of one of the carry generation blocks is three stages. There may be other carry generation blocks that are of a size that is a whole number multiple of thr... | 01/29/2008 |
| 7313586 | Adder-subtracter circuit An adder-subtracter circuit being adapted to process two binary input numbers in order to generate the sum or the difference of the two processed numbers depending on the state of a subtract input signal. The circuit has the capability to feed back the result of the... | 12/25/2007 |
| 7299355 | Fast SHA1 implementation Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which SHA1 multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. As described in this ... | 11/20/2007 |
| 7256612 | Programmable logic block providing carry chain with programmable initialization values A programmable logic block provides programmable initialization values for carry chains traversing the logic block, without consuming user logic resources. An exemplary programmable logic block includes two or more carry multiplexers coupled together to form a carry... | 08/14/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7219118 | SIMD addition circuit A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a sum of each set of binary numbers. Each set of numbers defines a disti... | 05/15/2007 |
| 7191205 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 03/13/2007 |
| 7185043 | Adder including generate and propagate bits corresponding to multiple columns An apparatus for adding a first value and a second value each including a plurality of bits includes combiner units, a carry creation unit and summation units. Bits corresponding to bit positions of the first and the second value form respective columns. Each of the... | 02/27/2007 |
| 7155473 | High-speed parallel-prefix modulo 2n-1 adders A parallel-prefix modulo 2n−1 adder that is as fast as the fastest parallel prefix 2n integer adders, does not require an extra level of logic to generate the carry values, and has a very regular structure to which pipeline registers can easi... | 12/26/2006 |
| 7152089 | Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks A circuit that performs a prefix computation. This circuit includes an N-bit prefix network of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . . , Y1} from N inputs {XN, . . . , X | 12/19/2006 |
| 7139789 | Adder increment circuit In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating wheth... | 11/21/2006 |
| 7111034 | Carry foreknowledge adder A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a un... | 09/19/2006 |
| 7085796 | Dynamic adder with reduced logic A dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added. The method for implementing the incentive adder users a novel X... | 08/01/2006 |
| 7035887 | Apparatus and method for data shifting A data shifter selects data from a plurality of data blocks to effectively “window” data contained within the blocks. A second stage of shifting may be implemented by selection among the resultants of the windowing step. Such a shifter may find use in a data ali... | 04/25/2006 |
| 7028069 | Dynamic circuit using exclusive states The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of ... | 04/11/2006 |
| 7016932 | Adders and adder bit blocks having an internal propagation characteristic independent of a carry input to the bit block and methods for using the same Bit blocks for an adder are provided which include a first bit stage that generates a first bit associated propagation characteristic (bapc). The bapc is independent of a carry input to the bit block from another bit block of the adder. Additional bit stages may be ... | 03/21/2006 |
| 7003545 | High performance carry chain with reduced macrocell logic and fast carry lookahead A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B... | 02/21/2006 |
| 6970899 | Calculating unit and method for subtracting Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing through the adder block. Depending on the carry pass output signal, a ... | 11/29/2005 |
| 6965910 | Calculating unit and method for adding A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder block, which determines whether a carry passes fully through the respective adder block. If it is determined t... | 11/15/2005 |
| 6941421 | Zero delay data cache effective address generation A method and system for accessing a specified cache line using previously decoded base address offset bits, stored with a register file, which eliminate the need to perform a full address decode in the cache access path, and to replace the address generation adder m... | 09/06/2005 |
| 6912560 | Adder with improved overflow flag generation An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at lea... | 06/28/2005 |
| 6836147 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 12/28/2004 |
| 6529931 | Prefix tree adder with efficient carry generation An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. In accordance with an illustrative embodiment of the invention, the prefix trees are interconnected such tha... | 03/04/2003 |
| 6496846 | Conditional carry encoding for carry select adder The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of b... | 12/17/2002 |
| 6205463 | Fast 2-input 32-bit domino adder In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section... | 03/20/2001 |
| 6188240 | Programmable function block A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first ... | 02/13/2001 |
| 5943251 | Adder which handles multiple data with different data types An adder circuit includes various methods to control the carry bit at data boundaries when attempting to process multiple data of multiple types. One method is to generate both propagate and generate signals from the input data and modified propagate and ... | 08/24/1999 |
| 5933362 | Method of adding two binary numbers and binary adder used therein An adder has a carry signal generation block for producing carry generation signal bits representative of carry bits resulted from augend signal bits and addend signal bits and carry propagation signal bits representative of carry bits resulted from the a... | 08/03/1999 |
| 5878973 | Tool for peeling turntable polishing cloth A peeling tool for peeling a polishing cloth from a turntable includes a cloth pinching member for pinching a polishing cloth, and a cylindrical take-up cylinder having a cloth insertion slit formed in its outer peripheral surface. Cloth pinching portions... | 03/09/1999 |
| 5877973 | Logic operation circuit and carry look ahead adder An 8-bit CLA adder is constructed for inputting 4 lower bits a3:0,b3:0 and 4 upper bits a7:4,b7:4 of two input signals to the two 4-bit full adders 2,12 and a carry c-1 to the lowest bit the full adder of the first-stage 2 to generate carries c3,c7 corres... | 03/02/1999 |
| 5629886 | Method and structure for providing fast propagation of a carry signal in a field programmable gate array A carry logic circuit for a field programmable gate array (FPGA) which allows a carry input signal to be propagated through the carry logic circuit without passing through a multiplexer of another series connected circuit element. The carry logic circuit ... | 05/13/1997 |
| 5619442 | Alternating polarity carry look ahead adder circuit A carry look ahead circuit is implemented such that only one gate delay is incurred in calculating the carry output after the carry input becomes valid. The carry input and the carry output have opposite logical polarities. "Odd" carry look ahead stages a... | 04/08/1997 |
| 5581497 | Carry skip adder with enhanced grouping scheme An adder is described. The adder generates a block generate signal after one domino gate delay. The adder can also generate a carry out signal, generate a first plurality of sum signals in response to the carry out signal, generate a block generate signal... | 12/03/1996 |
| 5544085 | Fast adder chain A fast adder chain for adding together at least one pair of digital words and including a plurality of cascaded adder blocks. Each block having computation adders for obtaining the pseudosum of said pair of digital words and latches for storing and transm... | 08/06/1996 |
| 5504698 | Compact dual function adder A compact dual function adder circuit for providing both an addition operation for adding an input m-bit word to an input n-bit word, wherein m | 04/02/1996 |
| 5477480 | Carry look ahead addition method and carry look ahead addition device A carry look ahead addition device includes a carry generation/propagation term generator which receives input of two numbers each having a length of n (positive integer) bits and generates the carry generation term and the carry propagation term for each... | 12/19/1995 |
| 5357457 | Adder with carry look ahead circuit An adder circuit for adding two 16-bit data to each other includes 16 full adders and three carry look ahead circuits. A plurality of full adders excluding two ones provided on the least significant bit side and two ones provided on the most significant b... | 10/18/1994 |
| 5337269 | Carry skip adder with independent carry-in and carry skip paths A carry skip adder uses independent paths for propagating a skip carry bit and a carry-in bit. Propagation of the carry-in bit is inhibited during a first portion of the clock cycle to prevent spurious carry-in signals from affecting the operation. During... | 08/09/1994 |
