Quotables
"Man will not fly for 50 years."
Wilbur Wright ; 1901
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8244791 | Fast carry lookahead circuits A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path. ... | 08/14/2012 |
| 8086657 | Adder structure with midcycle latch for power reduction A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from... | 12/27/2011 |
| 7899860 | Method and system for high-speed floating-point operations and related computer program product A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this b... | 03/01/2011 |
| 7743085 | Configurable IC with large carry chains Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable... | 06/22/2010 |
| 7680874 | Adder An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15th digit to the 16th digit in the result of addition from the 1st digit to the 16th digit of the input data is generat... | 03/16/2010 |
| 7613763 | Apparatus and method for converting, and adder circuit An apparatus and method for converting a dual-rail input. The apparatus combines two useful operand bits and two auxiliary operand bits so that, in a data mode, two output operands of three output operands have a value which is different from that of the third outpu... | 11/03/2009 |
| 7516173 | Carry-skip adder having merged carry-skip cells with sum cells A multi-bit adder includes a carry chain, a carry-skip network, sum cells, and a carry-sum cell. The carry chain propagates, generates, or kills carry-in bits. The carry-skip network is coupled to the carry chain to selectively skip the carry-in bits over at least o... | 04/07/2009 |
| 7440991 | Digital circuit Disclosed is a digital circuit which comprises input signals A[n−1:0], SH[log2n−1:0], and DAT[n−1:0], a barrel shifter for outputting data B[n−1:0] obtained by shifting the signal DAT by the bits of the signal SH, a group G·P·SUM computation sta... | 10/21/2008 |
| 7406495 | Adder structure with midcycle latch for power reduction A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from... | 07/29/2008 |
| 7395307 | Carry look-ahead circuit and adder using same A carry look-ahead circuit for an adder to decrease circuit size and power consumption. The carry look-ahead circuit is composed of 2-input NAND gates 101, 102, 2-input NOR gate 103, AND-NOR type composite gates 201, 202, OR-NAND type composite ... | 07/01/2008 |
| 7325024 | Adder circuit with sense-amplifier multiplexer front-end An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate... | 01/29/2008 |
| 7325025 | Look-ahead carry adder circuit A look-ahead carry adder circuit has multiple stages that are grouped into a carry generation blocks. The size of one of the carry generation blocks is three stages. There may be other carry generation blocks that are of a size that is a whole number multiple of thr... | 01/29/2008 |
| 7313586 | Adder-subtracter circuit An adder-subtracter circuit being adapted to process two binary input numbers in order to generate the sum or the difference of the two processed numbers depending on the state of a subtract input signal. The circuit has the capability to feed back the result of the... | 12/25/2007 |
| 7302460 | Arrangement of 3-input LUT's to implement 4:2 compressors for multiple operand arithmetic A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells.... | 11/27/2007 |
| 7299355 | Fast SHA1 implementation Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which SHA1 multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. As described in this ... | 11/20/2007 |
| 7290027 | Circuit suitable for use in a carry lookahead adder An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the fir... | 10/30/2007 |
| 7280056 | Sigma-delta converter and use thereof A sigma-delta converter has a signal input for receiving a data word. A clock signal input is designed to supply a clock signal. The sigma-delta converter includes a first clocked-operation accumulator stage whose input side is connected to the signal input, and at ... | 10/09/2007 |
| 7277909 | High speed adder Provided is an adder composed of (N+1) circuit stages in the ease of 2.sup.N bits. In the case of N=4 (that is, 16 bits), provisional carries that indicate the case where carry is produced from a low order bit and the case where no carry is produced therefrom are ge... | 10/02/2007 |
| 7275076 | Multiplication logic circuit A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length col... | 09/25/2007 |
| 7240085 | Faster shift value calculation using modified carry-lookahead adder Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outpu... | 07/03/2007 |
| 7237216 | Clock gating approach to accommodate infrequent additional processing latencies A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal... | 06/26/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7225218 | Apparatus and methods for generating counts from base values An apparatus for generating a plurality of counts is provided. A first adder is coupled to receive n least significant bits of a base count and a plurality of signals indicative of a plurality of values to be added to the base count, each of the plurality of values ... | 05/29/2007 |
| 7219118 | SIMD addition circuit A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a sum of each set of binary numbers. Each set of numbers defines a disti... | 05/15/2007 |
| 7213043 | Sparce-redundant fixed point arithmetic modules A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A ... | 05/01/2007 |
| 7205791 | Bypass-able carry chain in a programmable logic device A carry chain in a logic array block includes a first path connecting a first series of logic elements in the logic array block, where the logic elements in the first series is a subset of the set of logic elements in the logic array block. The carry chain also incl... | 04/17/2007 |
| 7206801 | Digital multiplier with reduced spurious switching by means of Latch Adders A digital Parallel Multiplier has a Partial Product Generator, a First Stage Adder Circuit and a Final Stage Adder Circuit. The spurious switching in the First Stage Adder Circuit may be substantially reduced by synchronizing the input signals to the Adders in First... | 04/17/2007 |
| 7206802 | Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry... | 04/17/2007 |
| 7194501 | Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folde... | 03/20/2007 |
| 7191205 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 03/13/2007 |
| 7191317 | System and method for selectively controlling operations in lanes A method and system for conditionally carrying out an operation defined in a computer instruction wherein a computer instruction is implemented on so-called packed operands; that is, operands containing a plurality of packed objects in respective lanes. An operation... | 03/13/2007 |
| 7188134 | High-performance adder An adder for use in summing two binary numbers in an arithmetic logic unit of a processor. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the spa... | 03/06/2007 |
| 7185043 | Adder including generate and propagate bits corresponding to multiple columns An apparatus for adding a first value and a second value each including a plurality of bits includes combiner units, a carry creation unit and summation units. Bits corresponding to bit positions of the first and the second value form respective columns. Each of the... | 02/27/2007 |
| 7152089 | Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks A circuit that performs a prefix computation. This circuit includes an N-bit prefix network of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . . , Y1} from N inputs {XN, . . . , X | 12/19/2006 |
| 7136888 | Parallel counter and a logic circuit for performing multiplication A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of co... | 11/14/2006 |
| 7124160 | Processing architecture having parallel arithmetic capability According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operand... | 10/17/2006 |
| 7111034 | Carry foreknowledge adder A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a un... | 09/19/2006 |
| 7089559 | Method, apparatus, and program for chaining server applications A mechanism is provided for chaining server applications. A chaining module is provided that receives a series of server applications and chains them together passing the output of one to the input of the next. The series of server applications may be passed to the ... | 08/08/2006 |
| 7085796 | Dynamic adder with reduced logic A dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added. The method for implementing the incentive adder users a novel X... | 08/01/2006 |
| 7085798 | Sense-amp based adder with source follower pass gate evaluation tree A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amp... | 08/01/2006 |
