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| Number | Title | Issue Date |
| 8073830 | Expanded text excerpts A system provides a list of search results, where one of the search results in the list of search results includes a snippet from a corresponding search result document. The system receives selection of the snippet and provides an expanded snippet based on the selec... | 12/06/2011 |
| 7716270 | Carry-ripple adder A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit h... | 05/11/2010 |
| 7302460 | Arrangement of 3-input LUT's to implement 4:2 compressors for multiple operand arithmetic A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells.... | 11/27/2007 |
| 7290026 | Low-power high-speed 4-2 compressor with minimized transistor count A circuit for use in a microprocessor, comprising a 4-2 compressor circuit having a full adder formed of dual XOR/XNOR cells and a 2-1 MUX. The full adder uses minimum sized XOR/XNOR cells. ... | 10/30/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7191205 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 03/13/2007 |
| 7058678 | Fast forwarding ALU An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second binary number comprise: a first arithmetic logic unit (ALU) operating... | 06/06/2006 |
| 7049849 | Signal transmission circuits that use multiple input signals to generate a respective transmit signal A transmission circuit that conducts signals between integrated circuit devices includes a first driver circuit that generates a first transmit signal in response to first and second input signals, the first transmit signal being transmitted from the integrated circ... | 05/23/2006 |
| 7007059 | Fast pipelined adder/subtractor using increment/decrement function with reduced register utilization A fast pipelined adder/subtractor using increment/decrement functions with reduced register utilization. Embodiments of the present invention replace double width registers with incrementor elements, pipelined single width registers, and pipelined carry bits. This i... | 02/28/2006 |
| 7003545 | High performance carry chain with reduced macrocell logic and fast carry lookahead A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B... | 02/21/2006 |
| 6990508 | High performance carry chain with reduced macrocell logic and fast carry lookahead A programmable logic block in an integrated circuit comprising a plurality of macrocells, an AND-array, an OR-array, and a logic circuit. The plurality of macrocells may comprise logic that may be configured to (i) generate and propagate an inverted carry-input sign... | 01/24/2006 |
| 6989843 | Graphics system with an improved filtering adder tree A sample-to-pixel calculation unit in a graphics system may comprise an adder tree. The adder tree includes a plurality of adder cells coupled in a tree configuration. Input values are presented to a first layer of adder cells. Each input value may have two associat... | 01/24/2006 |
| 6990509 | Ultra low power adder with sum synchronization An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at the adder outputs by preventing signal transitions at the sum outputs... | 01/24/2006 |
| 6948051 | Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width A method and apparatus for reducing logic activity in a microprocessor which examines every instruction before it is executed and determines in advance the minimum appropriate datapath width (in byte or half-word quantities) necessary to accurately execute the opera... | 09/20/2005 |
| 6915323 | Macrocells supporting a carry cascade A programmable logic device includes a plurality of logic blocks. Each logic block includes a plurality of macrocells, with each macrocell being configurable to register a sum of product term output. In addition, the macrocells within each logic block are arranged f... | 07/05/2005 |
| 6912560 | Adder with improved overflow flag generation An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at lea... | 06/28/2005 |
| 6505226 | High speed parallel adder A parallel adder of the present invention operates at high speed and is reduced in size. The parallel adder outputs a carry signal from an inverter and a NAND-gate/NOR-gate to more rapidly generate the carry signal and selects a pass transistor after bein... | 01/07/2003 |
| 6446107 | Circuitry for performing operations on binary numbers Circuitry for adding a first binary number (A) having a plurality of bits (a0, a1, . . . ) to a second binary number (B) having a plurality of bits (b0, b1, . . . ) to produce a third binary number (A+B) having ... | 09/03/2002 |
| 6438571 | Adder circuit An adder circuit can perform of two integers respective consisted of n=k m bits at high speed with a smaller scale circuit than that of an adder circuit employing a carry look ahead circuit. The adder circuit includes m in number of k-bit adding circuits ... | 08/20/2002 |
| 6330581 | Apparatus and a method for address generation The present invention provides an apparatus and a method for address generation. In one embodiment, an apparatus for an address generation unit of an ALU (Arithmetic Logic Unit) of a microprocessor includes a first carry-propagate adder that adds a lower ... | 12/11/2001 |
| 6199090 | Double incrementing, low overhead, adder A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight ("first weight"). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receiv... | 03/06/2001 |
| 6188240 | Programmable function block A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first ... | 02/13/2001 |
| 6119141 | Resistive decoupling of function selection signals from input multiplexers in arithmetic logical units ALU The function selection signal of an ALU is resistively decoupled or serially coupled to the input multiplexers of the ALU. By producing delayed function selection signals and decoupling the delayed function signals from the input multiplexers, the input m... | 09/12/2000 |
| 5978826 | Adder with even/odd 1-bit adder cells An integrated circuit including an adder that is a series of one-bit cascaded adder cells. The circuits that implement the adder cells are not all alike. The adder cells are of two types: an even adder cell and an odd adder cell. The even adder cells rece... | 11/02/1999 |
| 5943251 | Adder which handles multiple data with different data types An adder circuit includes various methods to control the carry bit at data boundaries when attempting to process multiple data of multiple types. One method is to generate both propagate and generate signals from the input data and modified propagate and ... | 08/24/1999 |
| 5912833 | Carry increment adder using clock phase A carry increment adder (CIA) using a clock phase in which the CIA performs at an increased speed but uses a much smaller chip area than a general fast adder structure. In the CIA from 1 to N partial adder modules (RCA) which generate partial sum and part... | 06/15/1999 |
| 5912832 | Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders A method and apparatus for n-bit by n-bit multiplication is disclosed using paralleled 4-bit by 4-bit multipliers and cascaded adder structures. The cascaded adder structures may be used to produce non-pipelined, integer, n-bit by n-bit multipliers with h... | 06/15/1999 |
| 5898602 | Carry chain circuit with flexible carry function for implementing arithmetic and logical functions An improved arithmetic logic unit (ALU) of an erasable-programmable logic device (EPLD) with a flexible, programmable carry function allows a broad range of functions to be implemented. The inventive circuit utilizes a separately configurable carry chain ... | 04/27/1999 |
| 5822235 | Rectifying transfer gate circuit A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the so... | 10/13/1998 |
| 5818747 | Small, fast CMOS 4-2 carry-save adder cell A CMOS 4-2 carry-save adder cell implementation. A XNOR gate is used in the computation of SUM and CARRY. By using an XNOR gate, there are no possible input permutations which will cause any output in the SUM logic to be driven by two P-channel devices in... | 10/06/1998 |
| 5719802 | Adder circuit incorporating byte boundaries In accordance with the present invention, an adder is disclosed which combines byte boundary control signals with propagate-generate signal pairs immediately resulting from bit pairs of the input signals. Combining the byte boundary control signals with t... | 02/17/1998 |
| 5596520 | CMOS full adder circuit with pair of carry signal lines A full adder circuit has a plurality of full adders each provided for each bit. Each full adder has: a calculation block (31a) responsive to a first carry signal (C) given by a preceding stage bit as a differential signal and two external input data (A1, ... | 01/21/1997 |
| 5523963 | Logic structure and circuit for fast carry Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions whic... | 06/04/1996 |
| 5485415 | Digital integrating circuit device To provide a digital integrating circuit which can increase speed by preventing the influence of a delay in carry propagation and can obtain an accumulated value for each section at a higher sampling frequency, the carry holding type adder 4 and the carry... | 01/16/1996 |
| 5481206 | Circuit for fast carry and logic Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions whic... | 01/02/1996 |
| 5390135 | Parallel shift and add circuit and method An apparatus for combining the contents of an X register, shifted by m places, with the contents of a Y register to generate a result Z. The functional unit can also be configured to perform parallel operations on sub-operands in the X and Y registers. Th... | 02/14/1995 |
| 5239499 | Logical circuit that performs multiple logical operations in each stage processing unit A logical circuit comprises a plurality of stage processing units, each of which includes a logical operation processing unit and a carry signal transmission controlling unit. The logical operation processing unit carries out a logical operation process o... | 08/24/1993 |
| 5224065 | Arithmetic operation unit having bit inversion function A bit-inversion arithmetic operation unit comprises a first carry signal line for propagating a carry signal from a more significant bit position side to a less significant bit position side, and a second carry signal line for propagating a carry signal f... | 06/29/1993 |
| 5197140 | Sliced addressing multi-processor and method of operation A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. An addressing scheme, called sliced addressing, is... | 03/23/1993 |
| 5189635 | Digital data processing circuit A digital data processing circuit includes an adder circuit supplied with input data in a time-division multiplexed manner over a plurality of signal lines. The adder circuit is capable of executing additions at an optimum processing speed depending on th... | 02/23/1993 |
