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| Number | Title | Issue Date |
| 8099451 | Systems and methods for implementing logic in a processor Systems, methods and media for implementing logic in the arithmetic/logic unit of a processor are disclosed. More particularly, hardware is disclosed for computing logical operations with minimal hardware by organizing the execution unit such that the propagate and ... | 01/17/2012 |
| 7290026 | Low-power high-speed 4-2 compressor with minimized transistor count A circuit for use in a microprocessor, comprising a 4-2 compressor circuit having a full adder formed of dual XOR/XNOR cells and a 2-1 MUX. The full adder uses minimum sized XOR/XNOR cells. ... | 10/30/2007 |
| 7228325 | Bypassable adder An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the ... | 06/05/2007 |
| 7185042 | High speed, universal polarity full adder which consumes minimal power and minimal area A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding extra inverters or extra transistors. The cell makes liberal use of ... | 02/27/2007 |
| 7085796 | Dynamic adder with reduced logic A dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added. The method for implementing the incentive adder users a novel X... | 08/01/2006 |
| 7043520 | High-speed/low power finite impulse response filter A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response f... | 05/09/2006 |
| 6904447 | High speed low power 4-2 compressor A high speed low powered 4-2 compressor according to the present invention performs an XOR/XNOR operation of input data by using a single input type NAND/NOR logic circuit and a dual input type NAND/NOR logic circuit. Thus, delays to generate complementary signals a... | 06/07/2005 |
| 6836147 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 12/28/2004 |
| 6505226 | High speed parallel adder A parallel adder of the present invention operates at high speed and is reduced in size. The parallel adder outputs a carry signal from an inverter and a NAND-gate/NOR-gate to more rapidly generate the carry signal and selects a pass transistor after bein... | 01/07/2003 |
| 6199090 | Double incrementing, low overhead, adder A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight ("first weight"). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receiv... | 03/06/2001 |
| 6188240 | Programmable function block A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first ... | 02/13/2001 |
| 6148034 | Apparatus and method for determining video encoding motion compensation vectors An MPEG-1 or an MPEG-2 motion compensation vector encoder circuit achieves smaller circuit area, and hence lower cost, by using circuitry, including ROMs, designed to implement residue arithmetic to calculate sum squared error in a parallel pipelined fash... | 11/14/2000 |
| 5923205 | Semiconductor arithmetic circuit A semiconductor arithemetic circuit which performs calculation of an analog vector with a high accuracy at a high speed. A semiconductor arithemetic circuit having a plurality of MOS type transistors, wherein the source electrodes are connected to one ano... | 07/13/1999 |
| 5920498 | Compression circuit of an adder circuit An adder circuit includes a 4-2 compression circuit in which a NAND signal of a first input signal and a second input signal and an exclusive-OR signal of the first and second signals are produced. When the exclusive-OR output is true, a third signal is o... | 07/06/1999 |
| 5896308 | Combinational logic circuit The present invention relates to a combinational logic circuit including at least a pair of inputs and an output line; at least a first module and a symmetrical module; the first module including a parallel cell and a series cell; the parallel cell includ... | 04/20/1999 |
| 5818747 | Small, fast CMOS 4-2 carry-save adder cell A CMOS 4-2 carry-save adder cell implementation. A XNOR gate is used in the computation of SUM and CARRY. By using an XNOR gate, there are no possible input permutations which will cause any output in the SUM logic to be driven by two P-channel devices in... | 10/06/1998 |
| 5687107 | Exclusive-OR gate, an inverted type selector, and adders A new type exclusive-OR gate and an inverted type selector are composed using a cascaded connection of two p-type MOSFETs between a positive terminal of a power supply and an signal output terminal, and a cascaded connection of two n-type MOSFETs between ... | 11/11/1997 |
| 5648925 | Optimized operand formatting same A digital operand formatting stage that includes a first inverting means, a second inverting means having an input that is connected to the input of the first inverting means, and a third inverting means having an input that is connected to the output of ... | 07/15/1997 |
| 5617345 | Logical operation circuit and device having the same A logical operation circuit performing a logic operation on inputs includes a plurality of adders arranged in a tree structure. The plurality of adders includes first-type adders and second-type adders. The first-type adders are adders which receive posit... | 04/01/1997 |
| 5373459 | Floating point processor with high speed rounding circuit In an arithmetic processor, second data are subtracted from first data to derive a first overflow signal. The sum of the second data and "1" is subtracted from the first data to derive another overflow signal. The magnitude relation between the first and ... | 12/13/1994 |
| 5349250 | Logic structure and circuit for fast carry Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions whic... | 09/20/1994 |
| 5295090 | Logic structure and circuit for fast carry Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions whic... | 03/15/1994 |
| 5267187 | Logic structure and circuit for fast carry Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions whic... | 11/30/1993 |
| 5233233 | Multiplexer for use in a full adder having different gate delays The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal. The select gate includes a first gate for receiving and transferring a first logic signal to an output node, and a second gate for receiving and tran... | 08/03/1993 |
| 5206828 | Special carry save adder for high speed iterative division A special carry save adder includes structure for performing multiple addition operations, common input structure to the structure for performing multiple addition operations, and mixing structure for selecting the desired result of the multiple addition ... | 04/27/1993 |
| 4970677 | Full adder circuit with improved carry and sum logic gates First and second input gates and an input inverter are provided for preprocessing respectively a plurality of input signals and an additional input signal, in addition to a carry gate and a sum gate. The first input gate is connected to each of a pluralit... | 11/13/1990 |
| 4942548 | Parallel adder having removed dependencies A methodology to perform binary addition. An operand A and an operand B are presented as input and an operation is performed that respects the laws of the binary addition. The operation is performed with the use of pseudo generate signals, pseudo transmit... | 07/17/1990 |
| 4931981 | Multi-place ripple-carry adder A multi-place ripple-carry adder adapted for CMOS technology incorporates two types of adder cells in which the adder cells of a first type receive two operand inputs and an inverted carry input signal and produce outputs corresponding to a sum signal and... | 06/05/1990 |
| 4905179 | CMOS cell for logic operations with fast carry The elementary adder, as far as carry propagation is concerned, has two circuit branches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated when two operands have opposite logic levels, in which case it transfers complemented in... | 02/27/1990 |
| 4901269 | Multiple-stage carry-select adder having unique construction for initial adder cells An adder, operating on the carry-select principle, provides for the transmission of two carry signals (c-0, c-1) and incorporates only one half-added (HA1) for the formation of the sum signal. Every adder stage (AS) of the adder is composed of an initial ... | 02/13/1990 |
| 4897808 | Adder capable of usual addition and reverse carry addition An adder being adapted to switch by a control signal the respective functions of one terminal issuing a carry output and the other terminal given a signal thereto as a carry input, so that the adders for a plurality of bits are used to be realizable of an... | 01/30/1990 |
| 4897809 | High speed adder An improved cascadable adder (11) which, through the use of merged logic, provides high speed operation in the presence of input loading and internal fan-out limitations. The invention may be implemented in gallium arsenide technology and includes a first... | 01/30/1990 |
| 4893269 | Adder cell for carry-save arithmetic An adder cell in which the sum signal and the carry signal are formed with equal speed is provided for employment in "carry-save" adders, wherein the sum signal and the carry signal are separately forwarded to separate inputs of following adder cells. The... | 01/09/1990 |
| 4887233 | Pipeline arithmetic adder and multiplier A fast pipeline adder comprising a plurality of registered adder rows. In one embodiment, additions in the pipeline are realized in reclocked half adders. In another embodiment, modified adders are employed which accept two carry inputs and develop two ca... | 12/12/1989 |
| 4853887 | Binary adder having a fixed operand and parallel-serial binary multiplier incorporating such an adder Binary adder having a fixed operand and a parallel-serial binary multiplier incorporating such an adder. The multiplier comprises a dedicated adder, whose elements (transistors, logic gates, etc.) are wired to incorporate the value of the fixed operand B.... | 08/01/1989 |
| 4839849 | Ripple-carry adder An adder cell for a ripple-carry adder, suitable for use in an integrated circuit employing CMOS technology, has a gate arrangement for two input variables and a carry input signal, with outputs for sum and carry signals, in accordance with the signals pr... | 06/13/1989 |
| 4831578 | Binary adder A binary adder stage in which the two binary inputs are logically combined to produce the Exclusive-OR, the Exclusive-NOR, the NAND and the NOR functions of the two inputs. The carry-input signal is then used to control the generation of the sum output an... | 05/16/1989 |
| 4802112 | MOS transistor circuit When a carry signal generated in an n-th bit is propagated to an (n+1)th bit, two n-MOS transistors (12n+1 and 13n+1) connected by a signal line (Cn) are turned on to prompt transition of the signal line (Cn) to... | 01/31/1989 |
| 4766565 | Arithmetic logic circuit having a carry generator An inverting full adder circuit for use in a ripple-carry adder or arithmetic logic unit (ALU) which includes a plurality of similar full adder stages connected in series such that the carry delay from one stage to the next is minimized, and which require... | 08/23/1988 |
| 4733365 | Logic arithmetic circuit A logic arithmetic circuit comprising first through sixth transistors, the first through third being P-channel transistors and the fourth through sixth being N-channel transistors. The gates of the first and sixth transistors are supplied by a synchronizi... | 03/22/1988 |
