Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 7565392 | Single-level parallel-gated carry/majority circuits and systems therefrom A carry/majority circuit, comprising a plurality of differential transistor pairs coupled in parallel and forming a pair of output nodes, with a single parallel gated level. Current is steered through a leg of the transistor pair having a higher input voltage. ... | 07/21/2009 |
| 7155474 | Current-mode multi-valued full adder in semiconductor device A full adder in a semiconductor device, includes a reference current generation unit for generating a reference current, a carry generation unit for generating a threshold current for generating a carry in response to the reference current and for generating the car... | 12/26/2006 |
| 7085796 | Dynamic adder with reduced logic A dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added. The method for implementing the incentive adder users a novel X... | 08/01/2006 |
| 5990703 | Apparatus and method for a low power latchable adder A high speed, low power 3-2 adder (300, 500) with latchable outputs comprises a most significant bit (MSB) adder circuit (100) and a least significant bit (LSB) adder circuit (200). MSB adder circuit (100) includes three differential data inputs (A1, B1, ... | 11/23/1999 |
| 5812521 | Static adder using BICMOS emitter dot circuits A parallel static adder for adding two n-bit operands, the adder including half-sum circuitry, summing circuitry, and carry look-ahead circuitry. The half-sum circuitry receives a pair of same-order bits from the two n-bit operands, and generates a plural... | 09/22/1998 |
| 5717622 | Selecting circuit including circuits having different time constants to which each of a plurality of input signals is applied, and adding circuit using the same A selecting circuit is formed of two tristate gates. The size of each of a plurality of transistors configuring a tristate gate processing a signal having a shorter delay time is set smaller than the size of each of a plurality of transistors configuring ... | 02/10/1998 |
| 5265044 | High speed arithmetic and logic generator with reduced complexity using negative resistance A technique for generating a carry, AND, OR, NAND, NOR, INVERTING logic and sum and carry: operation in a one or at most two device delay by employing negative differential resistance devices. Circuits implemented with this technique are not only extremel... | 11/23/1993 |
| 5175703 | High speed full adder and method A high-speed current mode 2-bit full adder using ripple carry with two full adders using three-levels of series gating, a bandgap reference voltage generator, two sum out buffers, and a carry out buffer. The method for the addition of an input carry bit a... | 12/29/1992 |
| 5132921 | High speed digital computing system A digital computing system comprises first, second, third, fourth, fifth, and sixth multi-bit binary signal sources and first and second binary adders. Each binary adder has a plurality of parallel stages equal in number to the bits of the signals. Each s... | 07/21/1992 |
| 4918640 | Adder cell having a sum part and a carry part An adder cell having a sum part and a carry part, whereby the sum part and the carry part each contain differential amplifiers having exclusively bipolar or ECL technology as well as differential amplifiers having mixed bipolar MOS transistors. The proces... | 04/17/1990 |
| 4916653 | Adder using multi-state logic A binary digital full adder as a component element of a digital circuit receives three binary signals including two input signals and a carry-in from the lower digit. The adder comprises a four-state logic converter for adding together the three binary si... | 04/10/1990 |
| 4831579 | Full adder circuit having an exclusive-OR circuit A logic operation circuit includes an exclusive-OR circuit for receiving first and second logic sum signals of preceeding stages, a sum signal selection circuit for selectively generating a carry output signal or an inverted signal thereof as a carry outp... | 05/16/1989 |
| 4740907 | Full adder circuit using differential transistor pairs A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuit... | 04/26/1988 |
| 4718035 | Logic operation circuit having an exclusive-OR circuit A logic operation circuit includes an exclusive-OR circuit for receiving first and second input signals, a carry output signal selection circuit for selectively generating a sum signal or an inverted signal thereof as a carry output signal in accordance w... | 01/05/1988 |
| 4449197 | One-bit full adder circuit The present invention is a one-bit full adder circuit having a fast carry. The circuit may be implemented using integrated injection logic in which case the circuit comprises six NAND gates and two wired AND gates. Advantageously, there is only a single g... | 05/15/1984 |
| 4229803 | I2 L Full adder and ALU A minimum design I2 L full adder with carry look ahead capabilities has all arithmetic logic unit functions, including OR, AND, XOR and SUM generated within. The full adder is easily extended to an arithmetic logic unit where all logic function... | 10/21/1980 |
| 4215418 | Integrated digital multiplier circuit using current mode logic A parallel digital multiplier circuit fabricated in accordance with an advanced triple diffusion process providing feature geometry down to a minimum of two microns and junction depths of less than two microns, wherein a high packing density provided by t... | 07/29/1980 |
| 4122527 | Emitter coupled multiplier array A high speed multiplier array implemented with a current switch emitter follower logic gate employs an inverted carry signal internal to the array. External carry signals received by the array are first inverted for internal processing. This implementatio... | 10/24/1978 |
