Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 7991820 | One step binary summarizer The ONE STEP BINARY SUMMARIZER is a digital logic circuit. It is used for summarizing two binary numbers. It contains one Function Generator Module and one or more SUMMARIZER Units. For subtraction it is subtracting Register “A” from Register “B” and Registe... | 08/02/2011 |
| 7617269 | Logic entity with two outputs for efficient adder and other macro implementations An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a s... | 11/10/2009 |
| 7475105 | One bit full adder with sum and carry outputs capable of independent functionalities A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit inclu... | 01/06/2009 |
| 7401110 | System, method and apparatus for an improved MD5 hash algorithm An MD5 arithmetic unit including multiple carry look-ahead adders. The carry look-ahead adders are configured to execute substantially simultaneously. A method of executing an MD5 algorithm is also disclosed. ... | 07/15/2008 |
| 7395306 | Fast add rotate add operation A system and associated methodology for performing a fast add rotate add operation is disclosed. Two separate addition functions conventionally separated by a shift operation are performed as a single operation thereby reducing the number of acts and resources requi... | 07/01/2008 |
| 7386583 | Carry generator based on XOR, and conditional select adder using the carry generator, and method therefor A conditional select adder having a carry generating unit which generates a carry of two n-bit input data units X0-Xn-1, and Y0-Yn-1, and a sum generating unit which generates the sum of the input data, is provided. The ca... | 06/10/2008 |
| 7343578 | Method and system for generating a bitstream view of a design A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e.g., one or more of a PLD design's essential configuration bits) and a... | 03/11/2008 |
| 7336097 | Look-up table structure with embedded carry logic A programmable look-up-table (LUT) structure adapted for carry logic incrementer implementation in an integrated circuit, comprising: three or more data inputs and a carry-in input, said data inputs comprised of consecutive bits in a data string, said carry-in compr... | 02/26/2008 |
| 7330869 | Hybrid arithmetic logic unit Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: ... | 02/12/2008 |
| 7302460 | Arrangement of 3-input LUT's to implement 4:2 compressors for multiple operand arithmetic A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells.... | 11/27/2007 |
| 7290026 | Low-power high-speed 4-2 compressor with minimized transistor count A circuit for use in a microprocessor, comprising a 4-2 compressor circuit having a full adder formed of dual XOR/XNOR cells and a 2-1 MUX. The full adder uses minimum sized XOR/XNOR cells. ... | 10/30/2007 |
| 7290027 | Circuit suitable for use in a carry lookahead adder An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the fir... | 10/30/2007 |
| 7284029 | 4-to-2 carry save adder using limited switching dynamic logic A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry s... | 10/16/2007 |
| 7281140 | Digital throttle for multiple operating points A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline. The monitored activity is scaled according to the current operating point of the processor and a power state is determined from the sc... | 10/09/2007 |
| 7281117 | Processor executing SIMD instructions A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC | 10/09/2007 |
| 7266581 | Arithmetic circuit There is provided an arithmetic circuit for minimizing the delay of data path from the input of data to be operated to the output of the result of operation of data. To that end, the arithmetic circuit comprises a first selector to which one input data and a fixed d... | 09/04/2007 |
| 7233964 | Method and system for compositing three-dimensional graphics images using associative decision mechanism A method and system for compositing a plurality of three-dimensional Sub-Images by examining the Depth values of the Pixels corresponding to same spatial location in each Sub-Image and compositing the content of the Pixel having the greatest Depth value. The Depth v... | 06/19/2007 |
| 7233963 | Systems and methods for diffusing clipping error Systems and methods are provided for diffusing clipping error in a computing system. When a data set contains values which are to be restricted to a range, and the data set includes one or more values which are beyond the range, the invention provides methodology th... | 06/19/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7218139 | Programmable integrated circuit providing efficient implementations of arithmetic functions Efficient implementations of arithmetic functions in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate both an exclusive OR (XOR) functio... | 05/15/2007 |
| 7197691 | Reduced-latency soft-in/soft-out module Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-o... | 03/27/2007 |
| 7194501 | Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folde... | 03/20/2007 |
| 7185307 | Method of fabricating and integrated circuit through utilizing metal layers to program randomly positioned basic units A method of fabricating an integrated circuit. The integrated circuit has a semiconductor body. The method includes forming a plurality of basic units with the same component characteristic on the semiconductor body, and forming at least a layout layer to program th... | 02/27/2007 |
| 7167514 | Processing of quinary data A FIR filter in a Gigabit transceiver in which data words are represented in three bits: SIGN representing word sign, SHIFT representing requirement for a shift operation, and ZERO indicating whether the word is zero. An AND gate ANDs an input coefficient and the ZE... | 01/23/2007 |
| 7152089 | Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks A circuit that performs a prefix computation. This circuit includes an N-bit prefix network of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . . , Y1} from N inputs {XN, . . . , X | 12/19/2006 |
| 7124160 | Processing architecture having parallel arithmetic capability According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operand... | 10/17/2006 |
| 7085796 | Dynamic adder with reduced logic A dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added. The method for implementing the incentive adder users a novel X... | 08/01/2006 |
| 7085798 | Sense-amp based adder with source follower pass gate evaluation tree A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amp... | 08/01/2006 |
| 7058678 | Fast forwarding ALU An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second binary number comprise: a first arithmetic logic unit (ALU) operating... | 06/06/2006 |
| 7046698 | Communicating apparatus and communicating method A communicating apparatus performs an asynchronous communication with a base station. The communicating apparatus is provided with: a receiving device for receiving a down link signal, which is transmitted from the base station and in which a division signal is inse... | 05/16/2006 |
| 7024446 | Circuitry for arithmetically accumulating a succession of arithmetic values A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the u... | 04/04/2006 |
| 6999985 | Single instruction multiple data processing A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in respo... | 02/14/2006 |
| 6990508 | High performance carry chain with reduced macrocell logic and fast carry lookahead A programmable logic block in an integrated circuit comprising a plurality of macrocells, an AND-array, an OR-array, and a logic circuit. The plurality of macrocells may comprise logic that may be configured to (i) generate and propagate an inverted carry-input sign... | 01/24/2006 |
| 6961063 | Method and apparatus for improved memory management of video images A novel storage format enabling a method for improved memory management of video images is described. The method includes receiving an image consisting of a plurality of color components. Once received, the plurality of color components is converted to a mixed forma... | 11/01/2005 |
| 6954773 | Providing an adder with a conversion circuit in a slack propagation path In one embodiment of the present invention, a high-speed adder is provided. This adder may incorporate a conversion circuit in a slack propagation timing path to provide for improved performance. The present invention may be incorporated into single or multi-bit add... | 10/11/2005 |
| 6924664 | Field programmable gate array A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure. Each logic head includes a plurality of cascadable logic blocks that ca... | 08/02/2005 |
| 6912560 | Adder with improved overflow flag generation An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at lea... | 06/28/2005 |
| 6847228 | Carry logic design having simplified timing modeling for a field programmable gate array A configurable logic block (CLB) slice is provided that includes a single path for a carry input signal to propagate through the CLB slice as a carry output signal. This single path includes a multiplexer that is configured to receive the input signals (including th... | 01/25/2005 |
| 6832315 | Method of labelling an article A method of labelling an article, including a) choosing a first character string comprising an identification number chosen to represent an article or a given class of articles, the character string comprising two or more characters, b) expressing each character in ... | 12/14/2004 |
| 6820186 | System and method for building packets Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag use... | 11/16/2004 |
