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Class 708/685 - Parallel


Subclass of Class 708 - Electrical computers: arithmetic processing and calculating
Definition: Subject matter wherein the numerical digits are operated
No. of patents: 16
Last issue date: 08/02/2011


NumberTitleIssue Date
7991819Binary coded decimal addition
The binary coded decimal (BCD) adder circuit adds two BCD encoded operands, with an input carry bit, and produces a BCD encoded sum. The adder has three stages. The first stage receives two BCD encoded operands as inputs, groups the inputs into contiguous blocks of ...
08/02/2011
7299254Binary coded decimal addition
The binary coded decimal (BCD) adder circuit adds two BCD encoded operands, with an input carry bit, and produces a BCD encoded sum. The adder has three stages. The first stage receives two BCD encoded operands as inputs, groups the inputs into contiguous blocks of ...
11/20/2007
7213043Sparce-redundant fixed point arithmetic modules
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A ...
05/01/2007
6978290Carry ripple adder
A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for accepting two carry bits having the significance w. It also contains an output for a sum bit having the signific...
12/20/2005
5745399Decimal arithmetic apparatus and method
An apparatus for adding two BCD numbers, avoids the need for special adders with detection of carries between BCD digits. First, a sum without carries is generated, by forming the binary sum of the two numbers and an all-sixes pattern, without any carries...
04/28/1998
4805131BCD adder circuit
The binary coded decimal (BCD) adder circuit for adding two BCD encoded operands and for producing a BCD encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermediate sum vector and an intermediate carry vecto...
02/14/1989
4799181BCD arithmetic using binary arithmetic and logical operations
A binary arithmetic unit performs arithmetic operations on binary coded decimal (BCD) operands by converting the BCD digits to hexadecimal excess 3 digits, generating hexadecimal excess 6 partial product digits and modifying selected excess 6 partial prod...
01/17/1989
4498177M Out of N code checker circuit
An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators...
02/05/1985
4139894Multi-digit arithmetic logic circuit for fast parallel execution
A simple and fast arithmetic member for multi-digit numbers. For each digit a module is provided which receives the digits of corresponding significance and which first forms two output carry signals therefrom, i.e. one as if the relevant module always re...
02/13/1979
4138731High speed binary and binary coded decimal adder
A high speed binary and binary coded decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a binary coded decimal addition with only one processing of the adder. The partial adders are each compo...
02/06/1979
4118786Integrated binary-BCD look-ahead adder
An improved system for adding two numbers together. The numbers may be expressed either in binary form or in binary coded decimal form (wherein each decimal digit is represented by its equivalent four binary bits). By taking advantage of "don't care" deci...
10/03/1978
4094138Electronic chronograph
The chronograph comprises a device allowing to memorize at least two lapses of time and a subtraction device to effect the absolute difference between two lapses of time or time intervals which are memorized and preselected. The subtraction device include...
06/13/1978
4001570Arithmetic unit for a digital data processor
A digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format. Such adding and subtracting is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no s...
01/04/1977
4001567BDC corrected adder
A BCD corrected serial adder includes an adder circuit and an asynchronous programmable logic array (PLA) connected to an output of the adder circuit. Whenever the sum of two bytes exceeds the decimal number 9 in the addition mode, the PLA simultaneously ...
01/04/1977
3991307Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results
Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results. The correction is by logical gating which operates selectively and on-the-fly, that is, while the sum from ...
11/09/1976
3935438Decimal adder
A decimal adder has plural arithmetic stages, each for generating one new bcd digit, and a controller for all stages. Each stage has three, four-stage binary adders one as input receiver for one input bcd digit, one main adder and one as output corrector....
01/27/1976
 
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