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| Number | Title | Issue Date |
| 7254599 | Average code generation circuit Disclosed is a method and circuit for generating an average binary code from at least two input binary codes. The circuit may be employed in an integrated circuit having first and second circuits for generating binary codes am-1:0 and bm-1:0, r... | 08/07/2007 |
| 7167968 | Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data A method of pre-aligning data for storage during instruction execution improves performance by eliminating the cycles otherwise required for data alignment. The method can convert data between ASCII and Packed Decimal format, and between Unicode Basic Latin and Pack... | 01/23/2007 |
| 6832315 | Method of labelling an article A method of labelling an article, including a) choosing a first character string comprising an identification number chosen to represent an article or a given class of articles, the character string comprising two or more characters, b) expressing each character in ... | 12/14/2004 |
| 6226664 | Method and device for adding and subtracting thermometer coded data Two thermometer coded words having a most significant byte (MSB) and a least significant byte (LSB) are subtracted, and a check detects a borrowing condition. A first borrowing condition is detected if word B MSB is greater than word A MSB (12), and word ... | 05/01/2001 |
| 5751623 | Digital computer for adding and subtracting A method and apparatus for efficiently adding and subtracting multiple digit decimal numbers represented as a series of 8-bit bytes, each 8-bit byte representing one digit of a decimal number. In accordance with the present invention, numeric values are s... | 05/12/1998 |
| 5699287 | Method and device for adding and subtracting thermometer coded data For subtracting two thermometer coded words each having a most significant byte (MSB) and a least significant byte (LSB), a check is made to see if a borrowing condition exists. A first borrowing condition exists if word B MSB is greater than word A MSB (... | 12/16/1997 |
| 5687359 | Floating point processor supporting hexadecimal and binary modes using common instructions with memory storing a pair of representations for each value A computer system having multiple floating point modes and common instructions for each mode in order to implement operations in a mode independent manner. A computer system includes two floating point modes supported by a common set of instructions for i... | 11/11/1997 |
| 5086406 | Circuit arrangement for decimal arithmetic A circuit for performing decimal subtraction at high speed has an execution time which is independent of the existence of a borrow condition. The subtraction circuit is particularly suited for use in microcoded computer circuits.... | 02/04/1992 |
| 4866656 | High-speed binary and decimal arithmetic logic unit A combined binary and binary coded decimal (BCD) arithmetic logic unit (binary/BCD ALU) having a binary adder adapted to perform decimal operations on BCD data without impacting the performance of binary operations. The combined binary/BCD ALU has a look-... | 09/12/1989 |
| 4805131 | BCD adder circuit The binary coded decimal (BCD) adder circuit for adding two BCD encoded operands and for producing a BCD encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermediate sum vector and an intermediate carry vecto... | 02/14/1989 |
| 4638300 | Central processing unit having built-in BCD operation A CPU data path portion having an ALU, an adjuster unit, a shifter unit and a shift register unit is disclosed. The CPU is capable of selectively forming the sum or difference of a first BCD operand and a second BCD operand by arithmetically combining the... | 01/20/1987 |
| 4464716 | Digital data processing system using unique formatting techniques for performing arithmetic ALU operations A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplifi... | 08/07/1984 |
| 4384340 | Data processor having apparatus for controlling the selection of decimal digits of an operand when executing decimal arithmetic instructions A commercial instruction processor executes decimal arithmetic instructions on string decimal and packed decimal operands. A read only memory is responsive to control signals generated from the operation code portion of the instruction, a type signal from... | 05/17/1983 |
| 4138731 | High speed binary and binary coded decimal adder A high speed binary and binary coded decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a binary coded decimal addition with only one processing of the adder. The partial adders are each compo... | 02/06/1979 |
| 4125867 | Electronic calculator or microprocessor having a hexadecimal/binary coded decimal arithmetic unit An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having a hexadecimal/binary coded decimal format arithmetic unit for performing arithmetic operati... | 11/14/1978 |
