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"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 8122079 | Event counter A counting method and a counter using an integrated circuit memory area, including at least one step of storage of partial values in several words of identical memory sizes, the result of the counting being obtained by arithmetically adding the values contained in t... | 02/21/2012 |
| 7447727 | Recursive carry-select topology in incrementer designs A recursive carry-select substitution operation is used to optimize the design of an incrementer and similar logic devices. A carry look-ahead incrementer features XOR gates in which the XOR gates in one or more MSBs of the incrementer can be pushed back by substitu... | 11/04/2008 |
| 7437622 | Implementation-efficient multiple-counter value hardware performance counter An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based a... | 10/14/2008 |
| 7395305 | Method and relative circuit for incrementing, decrementing or two's complementing a bit string A method for incrementing, decrementing or two's complementing a first string of bits includes generating an auxiliary string of bits as a function of the first string, and logically combining the auxiliary string with the first string to generate a corresponding ou... | 07/01/2008 |
| 7349937 | Fast incrementer using zero detection and increment method thereof A fast incrementer using zero detection and an increment method thereof. The incrementer performs a logic combination on an operand, first logic state inclusion information for each b-bit group of the operand, flag information for each b-bit group of the operand, an... | 03/25/2008 |
| 7330868 | Data input apparatus and method A command for incrementing a numeric value is inputted by pressing a “2” key. A command for decrementing the numeric value is inputted by depressing an “8” key. At least one of a process for incrementing the numeric value by the amount of increment according... | 02/12/2008 |
| 7304987 | System and method for synchronizing switch fabric backplane link management credit counters A system and method are provided for resynchronizing backplane link management credit counters in a packet communications switch fabric. The method comprises: at an input port card ingress port, accepting information packets including cells and cell headers with des... | 12/04/2007 |
| 7272754 | Implementation-efficient multiple-counter value hardware performance counter An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based a... | 09/18/2007 |
| RE39578 | Pipelined carry-lookahead generation for a fast incrementer An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All... | 04/17/2007 |
| 7194500 | Scalable gray code counter The invention is a Gray code counter that uses a carry chain to determine the state of each bit of the counter. An additional bit that toggles at every clock is used to originate the carry chain, and to determine the counter direction. Then, a generic Gray count bit... | 03/20/2007 |
| 7171437 | Residue calculating unit immune to power analysis A power-residue calculating unit includes a K register connected to a first internal bus for once storing an intermediate calculation result to be discarded when a power-residue calculation is executed in accordance with a binary method. Therefore even when data to ... | 01/30/2007 |
| 7082453 | Long-period counter without carries The present invention is a counter that takes advantage of the speed and implementation of the LFSR counter by utilizing separate digit counters, each digit counter having a period that is a relative prime to the other digit counter periods. The total period will be... | 07/25/2006 |
| 7072930 | Binary counter Method for realizing a binary counter that changes a partly permuted data word stored in a non-volatile memory and including a counter and a working memory and storing a data word in the form of memory words in the non-volatile memory. The method further comprises r... | 07/04/2006 |
| 7047270 | Reporting a saturated counter value A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a ma... | 05/16/2006 |
| 7032100 | Simple algorithmic cryptography engine A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the de... | 04/18/2006 |
| 7007059 | Fast pipelined adder/subtractor using increment/decrement function with reduced register utilization A fast pipelined adder/subtractor using increment/decrement functions with reduced register utilization. Embodiments of the present invention replace double width registers with incrementor elements, pipelined single width registers, and pipelined carry bits. This i... | 02/28/2006 |
| 6990507 | Parity prediction for arithmetic increment function The present invention provides a method and apparatus to check the arithmetic increment function through prediction of the change in the bit-level parity of the result by means of a series of identical cells connected in a linear array. The array predicts the change... | 01/24/2006 |
| 6976047 | Skipped carry incrementer for FFT address generation A method and apparatus are used to generate FFT data addresses for a butterfly stage based upon a computation stage value. The method includes setting a selected bit of a binary word at a logical value, performing an addition operation by adding a logical “1” to... | 12/13/2005 |
| 6918024 | Address generating circuit and selection judging circuit An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the... | 07/12/2005 |
| 6907098 | Gray code counter A Gray code counter includes a holding circuit, first and second conversin circuit and an operation circuit. The holding circuit stores gray code signals and outputs the stored gray code signals in response to a clock signal. The first conversion circuit receives th... | 06/14/2005 |
| 6807556 | Method and apparatus for parallel carry chains An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output... | 10/19/2004 |
| 6804562 | Method and apparatus for overload-free driving of an actuator The invention relates to a method for overload-free driving of an actuator, in which an activation counter is incremented or decremented each time an activation request signal occurs, in which, depending on each occurrence of an activation request signal, a drive si... | 10/12/2004 |
| 6678711 | Incrementer/decrementer circuit Provided is an incrementing/decrementing apparatus that includes an adder having a first input and a second input, each of the first input and the second input comprising multiple bits. A first multi-bit signal is connected to the first input, and a secon... | 01/13/2004 |
| 6675188 | Counter control apparatus and control method thereof In a counter readout control apparatus comprising a plurality of counters, in which an upper-order counter performs a counting operation upon receiving a carry from a lower-order counter, this apparatus further comprising, a first means for resetting each... | 01/06/2004 |
| 6665698 | High speed incrementer/decrementer A high speed incrementer/decrementer design is presented that computes the propagate, generate, and kill signals which are used to compute carries and sums from the incrementer inputs. By setting one input to "0" and the carry-in to "1", the adder is used... | 12/16/2003 |
| 6591286 | Pipelined carry-lookahead generation for a fast incrementer An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next... | 07/08/2003 |
| 6516335 | Incrementer/decrementer having a reduced fanout architecture An incrementer/decrementer architecture having a reduced internal block fanout which is achieved efficiently in terms of the silicon area needed to implement the incrementer/decrementer. The incrementer/decrementer of the present invention is characterize... | 02/04/2003 |
| 6434588 | Binary counter with low power consumption Disclosed is a novel n-bit binary counter with low power consumption, which comprises a set of half-adders for adding a "1" to an n-bit input signal, which includes a lower-order m bit component and a higher-order (n-m) bit component, and a set of D (data... | 08/13/2002 |
| 6389444 | Adder apparatus having single adder for +1 and +2 functions In an adder apparatus, a first logic circuit performs a NOR operation upon a first bit of an n-bit input signal and a control signal to generate a first signal. A second logic circuit performs an OR operation upon the first bit of the n-bit input signal a... | 05/14/2002 |
| 6347327 | Method and apparatus for N-nary incrementor The present invention is an incrementor that receives as inputs a 32-dit 1-of-4 operand and a 1-of-2 increment control signal. For each dit of the operand, the present invention determines whether the increment control signal, which is treated as a carry ... | 02/12/2002 |
| 6279024 | High performance, low power incrementer for dynamic circuits A dynamic incrementer, implemented in the Self Resetting Complementary Metal Oxide Semiconductor (SRCMOS) circuit family, which internally performs single rail calculations and which generates the dual rail result using a strobing technique. The carry-loo... | 08/21/2001 |
| 6199090 | Double incrementing, low overhead, adder A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight ("first weight"). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receiv... | 03/06/2001 |
| 5917741 | Method and apparatus for performing floating-point rounding operations for multiple precisions using incrementers An integrated circuit and method for rounding a number in one of a first or second format to produce a rounded result wherein the number is represented by a set of bits. A first incrementer increments a first subset of the set of bits in response to being... | 06/29/1999 |
| 5889693 | CMOS sum select incrementor A method and apparatus for a CMOS inverter is provided for incrementing a first number by a one, three, or multiple of two. The incrementing unit includes an extract/restore unit for extracting a number of least significant bits from the first number, the... | 03/30/1999 |
| 5877972 | High speed incrementer with array method A high-speed incrementer array for incrementing a data input value by a binary one, wherein the data input value comprises a plurality of input bit values. The incrementer array includes a plurality of word lines, bit-line pairs, and sense amplifiers. The... | 03/02/1999 |
| 5835389 | Calculating the absolute difference of two integer numbers in a single instruction cycle The absolute difference of two signed or unsigned integer numbers (A, B) is calculated in one instruction cycle by bit-complementing the B operand, summing the A and bit-complemented B operands to obtain an intermediate result, detecting whether the inter... | 11/10/1998 |
| 5797117 | Month field division multiplexing solution for year 2000 computer date problem The invention provides a method for solving, for an interim period of up to seven years, what is commonly known as the year 2000 computer date problem. The method is based on utilizing the presently unused capacity of a two-digit computer month field, whi... | 08/18/1998 |
| 5784308 | Binary subtraction device For arithmetically combining the values of two numbers, for example adding and subtracting, comprising a data deletion system for deleting values from input data and outputting the result. The system has a deletion number detection apparatus for finding a... | 07/21/1998 |
| 5781464 | Apparatus and method for incrementing floating-point numbers represented in diffrent precision modes An incrementer for performing floating-point calculations is capable of incrementing a floating-point number represented in one of several different precision modes. The incrementer includes various incrementer portions coupled to one another and associat... | 07/14/1998 |
| 5682342 | High-speed counter In a counter circuit, an n-bit input signal is stored into a register in response to a clock pulse and then dumped out of the register in response to a subsequent clock pulse and divided into a lower m-bit component and a higher (n-m)-bit component. The l... | 10/28/1997 |
