Class 708/671 - Comparison

Subclass of Class 708 - Electrical computers: arithmetic processing and calculating
Definition: Subject matter for comparing by determining the mathematical
No. of patents: 84
Last issue date: 12/06/2011

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Number	Title	Issue Date
8073893	Method and/or system for comparing character expressions Embodiments of methods, apparatuses, devices and/or systems for manipulating character expressions to determine relationships among such character expressions. ...	12/06/2011
8037120	System and method for an efficient comparison operation of multi-bit vectors in a digital logic circuit An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodim...	10/11/2011
7958181	Method and apparatus for performing logical compare operations A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a secon...	06/07/2011
7620676	Lookup table and data acquisition method Input data is divided into a plurality of blocks, and the blocks are corresponded to each address of the lookup table, and a block is divided into a plurality of sections according to the change of the output data, and at this time position information to indicates ...	11/17/2009
7437402	Low-power, high-speed word comparator Apparatus and method for performing a high-speed, low-power bit-wise comparison of two digital words. For each bit, a bit comparator is shown, employing a compare node and a discharge node. After both nodes are charged, the discharge node is discharged and the condi...	10/14/2008
7434034	SIMD processor executing min/max instructions The result of eight find_min_16 of lookup-min_16, find_max_l6x, lookup_max_16 instructions may be stored in memory storage units of operand storage 24, using SIMD at addressing techniques detailed in U.S. patent application Ser. No. 10/929,992, filed Aug. 30,...	10/07/2008
7395304	Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then...	07/01/2008
7395303	Method and device for comparing binary data words A system and method for comparing binary data words are provided, which method includes splitting a first and a second data word (A, B) to be compared to one another into at least two subwords, one having high-order bits (hA, hB) and the other having low-order bits ...	07/01/2008
7352275	Device for comparing two words of n bits each The disclosure relates to a device for comparing two words, N and P, of n bits each. The device includes at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0=...	04/01/2008
7322032	Methods and apparatus for scheduling operation of a data source A computerized device has dynamically modifiable hardware, such as an ASIC, that performs queue-scheduling operations. The hardware incorporates a generic sorting processor (GSP) that is dynamically configurable to implement various sorting algorithms to meet specif...	01/22/2008
7284028	Comparator eliminating need for one's complement logic for signed numbers An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag genera...	10/16/2007
7242414	Processor having a compare extension of an instruction set architecture A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision ...	07/10/2007
7233964	Method and system for compositing three-dimensional graphics images using associative decision mechanism A method and system for compositing a plurality of three-dimensional Sub-Images by examining the Depth values of the Pixels corresponding to same spatial location in each Sub-Image and compositing the content of the Pixel having the greatest Depth value. The Depth v...	06/19/2007
7191359	Fail-safe controller A controller that receives an input of a status of an apparatus, executes predetermined arithmetic and logical operations, and outputs a control signal of the apparatus, and is equipped with a plurality of processors for executing the arithmetic and logical operatio...	03/13/2007
7124160	Processing architecture having parallel arithmetic capability According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operand...	10/17/2006
7103624	Comparator circuit and method A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data An−1A	09/05/2006
7089241	Classifier tuning based on data similarities A probabilistic classifier is used to classify data items in a data stream. The probabilistic classifier is trained, and an initial classification threshold is set, using unique training and evaluation data sets (i.e., data sets that do not contain duplicate data it...	08/08/2006
7085796	Dynamic adder with reduced logic A dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added. The method for implementing the incentive adder users a novel X...	08/01/2006
7054895	System and method for parallel computing multiple packed-sum absolute differences (PSAD) in response to a single instruction A system and method are presented in which multiple packed-sum absolute differences (PSAD) are computed in response to a single instruction. One embodiment of the system comprises a first register configured to store a first operand having data elements, and a secon...	05/30/2006
7020830	High speed add-compare-select operations for use in viterbi decoders Techniques are provided for the addition and comparison operations associated with a Viterbi decoding algorithm at substantially the same time. To this end, an operation of the type a±b>c±d (where a and b are to be added, c and d are to be added, and then the sums...	03/28/2006
7016931	Binary-number comparator A comparator for comparing binary numbers with N bits, where N>1, in which a plurality (200) of bit-to-bit comparators supplies a plurality of equality-difference signals, arranged in order of decreasing significance of the bits compared, to a matrix of trans...	03/21/2006
6938172	Data transformation for the reduction of power and noise in CMOS structures A data transformation algorithm is selectively applied to each data vector as it enters the pipelined structure. In a selection step, the algorithm compares the bit value of the new data vector with the corresponding bit values of the preceding data vector, and sums...	08/30/2005
6918024	Address generating circuit and selection judging circuit An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the...	07/12/2005
6907443	Magnitude comparator A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a third circuit coupled to the second circuit and coupled to receive a first operand of the operands to be c...	06/14/2005
6865590	Three input variable subfield comparation for fast matching The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number comparison. In one embodiment, variably-sized addresses are accommodated by augmenting a portion of the app...	03/08/2005
6826588	Method and apparatus for a fast comparison in redundant form arithmetic The present invention provides an efficient method for bypassing outputs while in redundant form to an arithmetic circuit that is capable of adding or subtracting numbers in redundant from and comparing the magnitudes of numbers received in redundant form for equali...	11/30/2004
6826290	Image processing apparatus and method and storage medium To provide a variety of methods for extracting digital watermark information from an image as correctly as possible. For example, a first pattern arrangement and a second pattern arrangement which is different from the first pattern arrangement for use in a calculat...	11/30/2004
6820109	System and method for predictive comparator following addition A computing system includes a plurality of full adders that each receives a bit-wise inversion of a bit of a first data, a bit of a second data, and a bit of a third data, respectively, and provides a sum output and a carry output. An exclusive-OR logic module recei...	11/16/2004
6819224	Apparatus and method for detecting a predetermined pattern of bits in a bitstream An apparatus for detecting a predetermined pattern of bits in a data bitstream includes a series of detecting elements (2-6), each detecting element in the series corresponding to a predetermined bit in the predetermined pattern. Each detecting element receiv...	11/16/2004
6813628	Method and apparatus for performing equality comparison in redundant form arithmetic A method and apparatus is disclosed to compare numbers for equality. The numbers represented in a redundant form, including numbers received from a bypass circuit are subtracted. More specifically, a complemented form is generated and supplied to an arithmeti...	11/02/2004
6795842	Method and apparatus for comparing two binary numbers with a power-of-two threshold Methods and apparatus for comparing two binary numbers with a power-of-two threshold are provided in accordance with the present invention. In one embodiment, a method for comparing two binary numbers with a power-of-two threshold includes the steps of generating ne...	09/21/2004
6763368	Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic A method and apparatus for adding numbers represented in redundant form or for subtracting numbers received in redundant form and for comparing results in redundant form for equality to an expected value. A redundant arithmetic circuit performs an arithmetic operati...	07/13/2004
6745215	Computer apparatus, program and method for determining the equivalence of two algebraic functions In a compiler or program proving or verification software code, it is often useful to analyse a computer program and one way in which this might be partially achieved is by comparing algebraic expressions to see if they are equivalent, i.e. to see if they are deriva...	06/01/2004
6701340	Double differential comparator and programmable analog block architecture using same A double differential comparator can be efficiently implemented utilizing a first comparator stage having a folded cascode with floating gate input terminals and clamped single-ended output, and a capacitively coupled input stage for transferring a weight...	03/02/2004
6691145	Computing circuit, computing apparatus, and semiconductor computing circuit A computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences and a semiconductor computing circuit achievable with simple circuitry and suita...	02/10/2004
6683530	Method and apparatus for performing a floating point compare operation A system, method and apparatus for comparing two floating point numbers is includes choosing a first floating point number and a second floating point number to be compared. The first number is sign extended one bit to create a first sign extended number....	01/27/2004
6658443	Method and apparatus for representing arithmetic intervals within a computer system One embodiment of the present invention provides a system for representing intervals within a computer system to facilitate efficient and sharp arithmetic interval operations. The system operates by receiving a representation of two intervals. These repre...	12/02/2003
6629118	Zero result prediction A zero result detector for detecting a zero result in the sum of a first operand A, a second operand B and a carry bit Cin operates by calculating A and A+1 and then comparing one of these with B (Cin=O, A; Cin=1, A+1) in dependence upon Cin. If the compa...	09/30/2003
6581087	Floating point adder capable of rapid clip-code generation In a floating point adder adding received two floating point data together and subtracting one such data from the other, before their exponent parts are matched in digit by a digit match unit the two data have their exponent parts compared and also their ...	06/17/2003
6564237	Arithmetic unit and data processing unit For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last da...	05/13/2003

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Class 708/671 - Comparison