Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 7870181 | Chinese abacus adder A Chinese abacus adder is disclosed. The Chinese abacus adder includes a B/A (binary to abacus) circuit, a P/A (parallel addition) circuit and a T/B (thermometric to binary) circuit. The Chinese abacus adder has a multiple radix calculating structure, which could re... | 01/11/2011 |
| 7853637 | Method and system for pipelining saturated accumulation and other loops with loop-carried dependencies Aggressive pipelining allows Field Programmable Gate Arrays (FPGAs) to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipelining and reduce the efficiency and speed of an FPGA im... | 12/14/2010 |
| 7743084 | Processing unit having multioperand decimal addition A multi-operand decimal adder is described that performs addition on multiple binary coded decimal (BCD) operands. The multi-operand decimal adder uses binary carry-save adders to produce intermediate sums and carries, and outputs a decimal result based on the inter... | 06/22/2010 |
| 7676537 | Address generation method for combining multiple selection results A method in an integrated circuit for generating an address value having a contiguous address range from a first selection result and a second selection result each being an one-of-k selection result includes selecting multiple multiplication factors being power-of-... | 03/09/2010 |
| 7555514 | Packed add-subtract operation in a microprocessor A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results... | 06/30/2009 |
| 7428567 | Arithmetic unit for addition or subtraction with preliminary saturation detection An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithm... | 09/23/2008 |
| 7424507 | High speed, low power, pipelined zero crossing detector that utilizes carry save adders A zero crossing detector employs carry save adders combined with fully pipelined logic to provide two-bit, three-bit or four-bit zero crossing detection. The detector offers the advantages of very high operating speed, very low power dissipation, low adder cell coun... | 09/09/2008 |
| 7395302 | Method and apparatus for performing horizontal addition and subtraction A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs... | 07/01/2008 |
| 7376691 | Arithmetic and logic unit using half adder The present invention discloses an ALU (Arithmetic Logic Unit) that can be operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using a half adder that uses a superconductor rapid single flux quantum logic device. The ALU using a half adder in... | 05/20/2008 |
| 7373369 | Advanced execution of extended floating-point add operations in a narrow dataflow A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the ... | 05/13/2008 |
| 7356554 | Variable fixed multipliers using memory blocks A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the... | 04/08/2008 |
| 7353163 | Exception handling method and apparatus for use in program code conversion A method of handling exceptions for use in an emulator (20) performing program code conversion. Registers (X) of a subject machine (11) being emulated (20) are represented by a pair of abstract registers (XA,XB) on the targ... | 04/01/2008 |
| 7322032 | Methods and apparatus for scheduling operation of a data source A computerized device has dynamically modifiable hardware, such as an ASIC, that performs queue-scheduling operations. The hardware incorporates a generic sorting processor (GSP) that is dynamically configurable to implement various sorting algorithms to meet specif... | 01/22/2008 |
| 7305543 | Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, e... | 12/04/2007 |
| 7302460 | Arrangement of 3-input LUT's to implement 4:2 compressors for multiple operand arithmetic A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells.... | 11/27/2007 |
| 7248665 | Prescaler Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof bei... | 07/24/2007 |
| 7243292 | Error correction using finite fields of odd characteristics on binary hardware Binary data representing a code word of an error-correcting code is used for calculating a syndrome, wherein a given portion of the binary data comprises k groups of data bits and represents a field element of the finite field GF(pk), p being an odd prime... | 07/10/2007 |
| 7240086 | Method of image format conversion and remote control device using the same A method of image format conversion and remote control device using the same. Addition terms for a first layer are derived from an image conversion table. Every two addition terms are assigned to an addition group, obtaining a plurality of addition groups. The two a... | 07/03/2007 |
| 7237013 | Network system including data socket components for accessing internet semaphores An improved method and system for accessing data from a semaphore in a computer system, through the use of a software component in an application. The method may involve multiple software components in a corresponding multiple of applications in a corresponding mult... | 06/26/2007 |
| 7228325 | Bypassable adder An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the ... | 06/05/2007 |
| 7225218 | Apparatus and methods for generating counts from base values An apparatus for generating a plurality of counts is provided. A first adder is coupled to receive n least significant bits of a base count and a plurality of signals indicative of a plurality of values to be added to the base count, each of the plurality of values ... | 05/29/2007 |
| 7213043 | Sparce-redundant fixed point arithmetic modules A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A ... | 05/01/2007 |
| 7205810 | Skew tolerant phase shift driver with controlled reset pulse width A phase shift driver for phase shifting an input clock signal at a first phase to generate an output signal at a second phase without missing subsequent input signals. Input logic circuitry of the phase shift driver may receive an input signal at a first phase. Outp... | 04/17/2007 |
| 7203714 | Logic circuit A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circu... | 04/10/2007 |
| 7197528 | Jacobian group element adder An objective is to obtain a Jacobian group element adder that can calculate addition in a Jacobian group of a Cab curve at a high speed, and can enhance practicality of the Cab curve. An algebraic curve parameter file A 10, and Gr... | 03/27/2007 |
| 7196942 | Configuration memory structure A configuration memory structure includes one or more distributed buffers cascaded together, the output of a first buffer driving an output data line and complementary output data line which terminate at the input of a succeeding buffer. The first buffer includes pr... | 03/27/2007 |
| 7197527 | Efficient arithmetic in finite fields of odd characteristic on binary hardware A method and apparatus for processing binary data representing field elements of an odd-characteristic finite field GF(pk). Binary data representing at least a portion of a field element of an odd-characteristic finite field GF(pk) is stored in... | 03/27/2007 |
| 7191333 | Method and apparatus for calculating a multiplicative inverse of an element of a prime field Techniques for implementing a digital signature algorithm in electronic computer hardware include computing the multiplicative inverse of a particular integer modulo a prime modulus by computing a first quantity modulo the prime modulus. The first quantity substanti... | 03/13/2007 |
| 7180253 | Method and system for generating multi-dimensional motion profiles A motion control system comprises control logic and a programming interface. The programming interface is configured to permit a user to specify a plurality of non-tangential path segments, and the control logic is configured to generate a plurality of additional co... | 02/20/2007 |
| 7164290 | Field programmable gate array logic unit and its cluster The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate un... | 01/16/2007 |
| 7159003 | Method and apparatus for generating sign-digit format of sum of two numbers A system and method for converting two binary digits into redundant sign-digit format. The system comprises a first adder for adding the binary digits together to generate a first result. A second adder adds an input carry from a previous digit to the first result a... | 01/02/2007 |
| 7155473 | High-speed parallel-prefix modulo 2n-1 adders A parallel-prefix modulo 2n−1 adder that is as fast as the fastest parallel prefix 2n integer adders, does not require an extra level of logic to generate the carry values, and has a very regular structure to which pipeline registers can easi... | 12/26/2006 |
| 7139900 | Data packet arithmetic logic devices and methods New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs the PADD operation in about one to two processor clock cycles is disc... | 11/21/2006 |
| 7111166 | Extending the range of computational fields of integers An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field,... | 09/19/2006 |
| 7085796 | Dynamic adder with reduced logic A dynamic parallel adder is provided which eliminates the positive (or negative) complimentary carry generate and propagate signal logic normally used to implement a conventional dynamic parallel added. The method for implementing the incentive adder users a novel X... | 08/01/2006 |
| 7061268 | Initializing a carry chain in a programmable logic device A logic circuit includes a first series of logic elements. Each logic element has a look-up table (LUT) and a dedicated adder to implement an arithmetic mode in the logic element. The logic circuit also includes a carry chain connecting the first series of logic ele... | 06/13/2006 |
| 7058678 | Fast forwarding ALU An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second binary number comprise: a first arithmetic logic unit (ALU) operating... | 06/06/2006 |
| 7053664 | Null value propagation for FAST14 logic Power consumption in NDL designs utilizing FAST14 technology can be controlled via the introduction and propagation of null value 1-of-N signals in selected areas of the logic. A shared logic tree circuit, which might perform an arithmetic function or a multiplexing... | 05/30/2006 |
| 7013036 | Image sensing apparatus and method of controlling image sensing Signals obtained from a sensor array that includes a plurality of energy transducers are processed. A converter used in this processing generates a plurality of converted signals by applying processing to signals from the energy transducers on a block by block basis... | 03/14/2006 |
| 6988121 | Efficient implementation of multiprecision arithmetic The present invention provides an efficient implementation of multiprecision arithmetic, such as for a microprocessor. For example, an implementation of multiprecision arithmetic is provided that eliminates condition codes, such as condition codes for a carry bit an... | 01/17/2006 |
