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A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
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| Number | Title | Issue Date |
| 7809784 | Apparatus and method for calculation of divisions and square roots Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {−1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial ... | 10/05/2010 |
| 7415494 | Divider apparatus and associated method A method of dividing, in a micro computer unit (MCU), a first binary number (N), having a first number of significant bits, by a second binary number (D), having a second number of significant bits, produces an integer result (Y). The method includes: determining th... | 08/19/2008 |
| 7362245 | Variable length coding method for data compression The present invention provides method of a variable length coding for data compression. The first coding algorithm is applied to encode the data with the value less than half of the calculated divider and another coding algorithm encoding the subtracted value of the... | 04/22/2008 |
| 7302460 | Arrangement of 3-input LUT's to implement 4:2 compressors for multiple operand arithmetic A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells.... | 11/27/2007 |
| 7277908 | Numeric processor, a numeric processing method, and a data processing apparatus or computer program incorporating a numeric processing mechanism Provided are methods, computer programs and data processing apparatus using numeric processing. Firstly, a corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, al... | 10/02/2007 |
| 7277540 | Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit... | 10/02/2007 |
| 7237000 | Speed of execution of a conditional subtract instruction and increasing the range of operands over which the instruction would be performed correctly A circuit which first shifts both a dividend and a divisor by an extra bit such that a 1-bit shift can be avoided after subtraction of the shifted values of dividend and the divisor, while performing a conditional subtraction instruction. The shifted divisor can con... | 06/26/2007 |
| 7127483 | Method and system of a microprocessor subtraction-division floating point divider The specification discloses a structure of and a method of operating a subtractive division (SD) cell where a portion of the partial remainder or estimated partial remainder directly indicates the next quotient digit. More particularly, by sufficiently constraining ... | 10/24/2006 |
| 7116738 | Data synchronization apparatus and method Disclosed is a method and apparatus for synchronizing data. In one embodiment, the apparatus includes a first communication link for transmitting first data and a second communication link for transmitting second data. A circuit coupled to the first and second commu... | 10/03/2006 |
| 6996598 | Calculation circuit for the division of a fixed-point signal A calculation circuit for the division of a fixed-point input signal comprising a sequence of digital data values having a width of n bits by an adjustable division factor 2a for the purpose of generating a divided fixed-point output signal, having a sign... | 02/07/2006 |
| 6912647 | Apparatus and method for creating instruction bundles in an explicitly parallel architecture An apparatus and method for creating instruction groups for explicitly parallel architectures is provided. The apparatus and method accept instruction groups as input and determine a number of each possible type of instruction in the instruction group. Based on the ... | 06/28/2005 |
| 6687728 | Method and apparatus for arithmetic operation and recording medium of method of operation An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of t... | 02/03/2004 |
| 6625633 | Divider and method with high radix A high radix divider capable of reducing the size of the circuit of a quotient/remainder judgement unit in a radix 2k restoring division divider for finding a quotient k number of bits at a time, comparing multiples B, 2B, and 3B of a divisor B... | 09/23/2003 |
| 6560624 | Method of executing each of division and remainder instructions and data processing device using the method A data processing device comprises an instruction decoding unit for decoding a code of either a division instruction or a remainder instruction applied thereto, the instruction code having a size field for storing data size information. When a control uni... | 05/06/2003 |
| 6546409 | Digital processing A digital processor and method for performing mathematical division in which performance degradation is mitigated by avoiding left shift and append (14) on the output of an ALU using pre-shift and append (18, 22) of the feedback from the quotient and rema... | 04/08/2003 |
| 6516457 | Method and system of data processing for designing a semiconductor device A data processing system for designing a customized master slice data includes the steps of consecutively locating a cell base block based on the design data, a plurality of dummy gate blocks, and a possible number of intermediate blocks in the area of th... | 02/04/2003 |
| 6477556 | Method and apparatus for arithmetic operation and recording medium of method of operation An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of t... | 11/05/2002 |
| 6477557 | Division circuit not requiring taking complements of divisor, dividend and remainder In division process of restoring type or non-restoring type, a partial remainder is compared with a divisor in terms of absolute value. If the partial remainder is larger or both are equal, a quotient of its column is regarded as 1 and if small, the quoti... | 11/05/2002 |
| 6317772 | Split remainder divider The invention provides computer apparatus for performing a division operation having a dividend mathematically divided by a divisor. The dividend and the divisor are split between a state machine and an array of carry save adders. The most significant bit... | 11/13/2001 |
| 6317771 | Method and apparatus for performing digital division A method and apparatus for performing digital division in an integrated circuit is described. The inventive digital division is implemented by a combination of subtraction, logical OR, and shifting operations. The logical OR operation requires only approx... | 11/13/2001 |
| 6286346 | Interruptable multiply and/or divide operations for use with an interrupt in a medical device processor A method and apparatus including conditional add and conditional add/subtract instructions are provided for use in the instruction set of a medical device instruction processor. More specifically, the conditional add and add/subtract instructions are prov... | 09/11/2001 |
| 6128639 | Array address and loop alignment calculations Division system and method support a hardware division address centrifuge to provide a flexible addressing scheme, and thus facilitates the reorganization and redistribution of data between remote and local memory blocks in a distributed memory massively ... | 10/03/2000 |
| 6108723 | System for implementing hardware automated control of burst mode data transfer over a communication link between devices operating in a block mode Burst-mode data transfers between a SCSI host bus adapter and at least one SCSI bus device interface adapter are implemented by hardware. For a first embodiment of the invention, the device interface adapter is equipped with a first, second and third data... | 08/22/2000 |
| 6094669 | Circuit and method for determining overflow in signed division A circuit and method are provided for dividing a signed numerator by a signed denominator and generating a signal when the division results in overflow condition. The circuit generates a partial remainder using a partial remainder generation circuit, and ... | 07/25/2000 |
| 6061781 | Concurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divide An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction in... | 05/09/2000 |
| 6047305 | Division circuit not requiring taking complements of divisor, dividend and remainder In division process of restoring type or non-restoring type, a partial remainder is compared with a divisor in terms of absolute value. If the partial remainder is larger or both are equal, a quotient of its column is regarded as 1 and if smaller, the quo... | 04/04/2000 |
| 5969976 | Division circuit and the division method thereof A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acqu... | 10/19/1999 |
| 5946223 | Subtraction/shift-type dividing device producing a 2-bit partial quotient in each cycle A first subtracting means subtracts divisor data from dividend data or partial remainder data. In parallel with the subtraction of the first subtracting means, a comparing means performs a comparison between the highest-3-bit data of the dividend or parti... | 08/31/1999 |
| 5903485 | Division by a constant A ripple through divider of a dividend by a constant is obtained by cascading a plurality of partial quotient tables. Each table incorporates the same divisor, so the divisor need not appear as an input. In one binary integer implementation for an n bit d... | 05/11/1999 |
| 5903486 | Device for digitally carrying out a division operation A device for the digital performance of a binary division according to a non-restoring type of division method chiefly comprises a circuit for the detection of null partial remainders during the division. Advantageously, combinational circuits are designe... | 05/11/1999 |
| 5870323 | Three overlapped stages of radix-2 square root/division with speculative execution In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quoti... | 02/09/1999 |
| 5815423 | Parallel processing division circuit A parallel processing division circuit performing fast divisions is provided. The division circuit includes a time control circuit, data register, data select circuit, subtractor, control signal generating unit, and outcome data generating circuit. The co... | 09/29/1998 |
| 5805489 | Digital microprocessor device having variable-delay division hardware The present invention is a variable-delay division (VDD) scheme implementable in hardware to execute signed and unsigned integer division and remainder operations in digital processor. The VDD scheme advantageously uses hardware utilized for multiplicatio... | 09/08/1998 |
| 5784307 | Division algorithm for floating point or integer numbers A computer-implemented algorithm for dividing numbers involves subtracting the divisor from the divided to generate a first intermediate result, which is then shifted by N-bits to obtain a remainder value. A portion of the remainder and a portion of the d... | 07/21/1998 |
| 5771182 | Bit-serial digital compressor A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pr... | 06/23/1998 |
| 5754460 | Method for performing signed division A method for signed integer division. Typically, the two's complement of the dividend is stored as an adjusted dividend. The upper half of the adjusted dividend is shifted left one bit. The LSB of the upper half of the adjusted dividend is set equal to th... | 05/19/1998 |
| 5675528 | Early detection of overflow and exceptional quotient/remainder pairs for nonrestoring twos complement division A system for the early detection of overflow or exceptional quotient/remainder pairs is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--if early overflow is not sig... | 10/07/1997 |
| 5644524 | Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive or This invention is an iterative technique for division. The divisor has N bits and the numerator has more than N bits, generally 2N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bi... | 07/01/1997 |
| 5615113 | Early signaling of no-overflow for nonrestoring twos complement division An early no-overflow signaling system and method is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--when a no-overflow condition is signaled, a subsequent plurality... | 03/25/1997 |
| 5596519 | Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR An iterative technique for division having a divisor of N bits and a numerator of more than N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not... | 01/21/1997 |
