Famous Patents
In 1879, Auguste Bartholdi received design patent number 11,023 titled "Design for a Statue". It was for the Statue of Liberty.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8407274 | Machine division Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical facto... | 03/26/2013 |
| 8352534 | Integer division circuit with allowable error An integer division circuit with allowable error is described, what a signal processing apparatus includes a pointer, a first left shifter, a second left shifter, a subtractor, a multiplier, and a right shifter. The pointer searches for a most significant non-zero b... | 01/08/2013 |
| 8346840 | Flexible accumulator for rational division A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created betw... | 01/01/2013 |
| 8255448 | Implementing division in a programmable integrated circuit device Division can be performed in a programmable integrated circuit device by computing a relatively small number of bits of the inverse of the divisor, and then programming multipliers in a specialized processing block of the device to perform multiplication of the divi... | 08/28/2012 |
| 8103712 | Method for performing a division operation in a system A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on th... | 01/24/2012 |
| 8060551 | Method and apparatus for integer division A method, arithmetic divider unit, and system are disclosed for dividing a dividend DZM . . . Z0 having a most significant bit ZM and a plurality of less significant bits ZM−1 through Z0 by a divisor RZN . . . Z0 | 11/15/2011 |
| 7801940 | Method for dividing a number by a fraction having a number in the form of a power of 2 at the numerator A method divides a number N1 by a number which can be written in the form 2n/k, n and k being whole numbers, and obtains a result N2. The result N2 is calculated by adding terms N1*Ki/2n-i for i ranging from 0 to N, ... | 09/21/2010 |
| 7516172 | Method for finding quotient in a digital system A fast division method which uses a smaller quotient digit set of {−1, 1} than {−1, 0, 1} that is used by known algorithms, therefore accelerates the speed of calculation. Partial remainders can be computed with the signals of remainders decided independently an... | 04/07/2009 |
| 7512648 | Division algorithm According to an aspect of the present invention, a quotient of a dividend divided by a divisor may be determined after reducing the dividend, divisor, and the remainder by using operations such as add, subtract, multiply, shift, AND which may result in reduced proce... | 03/31/2009 |
| 7321916 | Methods and apparatus for extracting integer remainders Methods and apparatus for determining a remainder value are disclosed. The methods and apparatus extract a residuary subset bitfield value from a binary value that is calculated using a scaled approximate reciprocal value that is associated with a compound exponent ... | 01/22/2008 |
| 7290025 | Calculation method for division of digital data, calculation apparatus for division of digital data, and program therefor A calculation speed of division carried out in a computer is increased. Partitioning means partitions a dividend y that is a 32-bit digital datum at every 8 bits from the least significant bit to generate four bit blocks y(1) to y(4). For the respectiv... | 10/30/2007 |
| 7277908 | Numeric processor, a numeric processing method, and a data processing apparatus or computer program incorporating a numeric processing mechanism Provided are methods, computer programs and data processing apparatus using numeric processing. Firstly, a corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, al... | 10/02/2007 |
| 7195523 | Electrical conductive path for a medical electronics device An electrical conductive path for medical electronic device generally includes a plurality of stackable molded non-conductive housing with each housing having a bore therethrough alignable with adjacent housing bores. The adjacent housings and define any combination... | 03/27/2007 |
| 7194499 | Pipelined divider and dividing method with small lookup table A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterativ... | 03/20/2007 |
| 7174358 | System, method, and apparatus for division coupled with truncation of signed binary numbers A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x... | 02/06/2007 |
| 7165086 | System, method, and apparatus for division coupled with rounding of signed binary numbers A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one ha... | 01/16/2007 |
| 7127590 | Reconfigurable VLIW processor Disclosed is a computer processor (300) comprising a plurality of processing units (FU_n) and communication means (302) by which the plurality of processing units are interconnected. The communication means is dynamically configurable based on a comput... | 10/24/2006 |
| 7117238 | Method and system for performing pipelined reciprocal and reciprocal square root operations A pipelined circuit configured to generate a Taylor's series approximation at least one function, preferably at least one of the reciprocal and the reciprocal square root, of an input value. The circuit is preloaded with or configured to generate a predetermined set... | 10/03/2006 |
| 7065546 | Method of performing quantization within a multimedia bitstream utilizing division-free instructions Methods for enhancing the performance of quantization operations by converting division operations to a combination of multiplication and shift operations, which are preferably performed on a processor supporting single-instruction multiple-data (SIMD) instructions.... | 06/20/2006 |
| 7027061 | Raster engine with multiple color depth digital display interface An improved raster engine adapted to render video data from a frame buffer to one of a plurality of disparate displays is disclosed which comprises an integral bounded video signature analyzer, a hardware cursor apparatus supporting dual scanned displays, programmat... | 04/11/2006 |
| 7013320 | Apparatus and method for remainder calculation using short approximate floating-point quotient An apparatus and method for creating lookup tables of approximate floating-point quotients which exactly represent the underlying value, within the range of the specified precision. The lookup tables are created without any extraneous data beyond what is needed and ... | 03/14/2006 |
| 7007058 | Methods and apparatus for binary division using look-up table Improved methods of operating a digital data processor to perform binary division include estimating reciprocals of at least selected divisors based on value accessed from a look-up table. For divisors in a first numerical range, the estimation can be based on a val... | 02/28/2006 |
| 6999985 | Single instruction multiple data processing A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in respo... | 02/14/2006 |
| 6996598 | Calculation circuit for the division of a fixed-point signal A calculation circuit for the division of a fixed-point input signal comprising a sequence of digital data values having a width of n bits by an adjustable division factor 2a for the purpose of generating a divided fixed-point output signal, having a sign... | 02/07/2006 |
| 6954214 | Efficient perceptual/physical color space conversion An imaging or other sensory reproduction system efficiently converts image or other sensory data between a perceptual color space (e.g., the sRGB color space) and a physical color space (unity gamma) or other perceptual/physical sensory models that are related by an... | 10/11/2005 |
| 6907442 | Development system of microprocessor for application program including integer division or integer remainder operations A microprocessor (10) comprises a compiler (4), which, for a source program including an integer division q=int(a÷b)(int( ) is a function discarding figures below decimal point in parentheses) for dividing integer a, expressed in N bits, by integer co... | 06/14/2005 |
| 6820108 | Method and apparatus to perform division in hardware In accordance with the preferred embodiment of the present invention a gain (A) is determined and utilized to cyclically converge upon a quotient (Q). More particularly, once A is determined, an estimate of QN is multiplied by Y to estimate {circumflex ov... | 11/16/2004 |
| 6795553 | Method and apparatus for modular inversion for information security and recording medium with a program for implementing the method Values X and N of n bits and a parameter t are input, then Y=X2−t mod N is calculated, then an extended binary GCD algorithm is executed for Y to obtain S=y−12k mod N and k, and R=S2−(k+t−2n) is calculated for S, t... | 09/21/2004 |
| 6728743 | Modulo remainder generator Apparatus for determining a remainder of a modulo division of a binary number made up of a string of bits, including a first plurality of substantially similar cells coupled in a linear sequence, the first plurality of cells including at least a first cell and a las... | 04/27/2004 |
| 6604121 | Digital division device and method using a reduced-sized lookup table Devices and methods are provided for estimating a high-precision quotient using a smaller-than-conventional lookup table. The devices include a numerator register feeding a numerator value (as a succession of bits or words) into a forward signal path. The... | 08/05/2003 |
| 6594681 | Quotient digit selection logic for floating point division/square root Quotient digit selection logic using a three-bit carry propagate adder is presented. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection ... | 07/15/2003 |
| 6578062 | Method and circuit for digital division A method and apparatus for calculating a quotient from a dividend and a divisor, wherein the divisor can be represented as (2N +2M) where N is greater than M, and wherein the dividend comprises an X-bit binary number divisible by the... | 06/10/2003 |
| 6167418 | Byte-switching arithmetic unit The present invention provides a byte-switching arithmetic unit comprising at least three stages, each of which has a plurality of two-input selectors operable in a predetermined minimum bit width unit, the byte-switching arithmetic unit having two inputs... | 12/26/2000 |
| 6138137 | Methods and apparatus for performing fast division operations in bit-serial processors Methods and apparatus for quickly dividing multiple-bit operands using bit-serial processors include strategies for eliminating the number of steps required to execute conventional division operations. According to an exemplary embodiment, a conditional s... | 10/24/2000 |
| 6125380 | Dividing method A method for dividing a dividend by a divisor and finding a dividing quotient and a dividing remainder is provided. The dividend has a low byte part and a high byte part and the divisor has a low byte part and a maximum digital value whose most significan... | 09/26/2000 |
| 6081824 | Method and apparatus for fast unsigned integral division A method and apparatus for fast unsigned integral division, utilized in compositing images, sounds or other data, is provided. Compositing utilizes a division step. The divisor is the value of two to the Nth power minus one. The division comprises the ste... | 06/27/2000 |
| 5907499 | Hardware implemented divider for binary numbers using a redundant binary representation A divider including a quotient decision circuit for making a sign decision of a quotient bit from upper three bits of a partial remainder, a redundant binary adder for adding a divisor to the partial remainder, a redundant binary subtractor for subtractin... | 05/25/1999 |
| 5903485 | Division by a constant A ripple through divider of a dividend by a constant is obtained by cascading a plurality of partial quotient tables. Each table incorporates the same divisor, so the divisor need not appear as an input. In one binary integer implementation for an n bit d... | 05/11/1999 |
| 5892348 | Matrix interpolation A method of memory matrix interpolation in an ASIC processor requires a reduced amount of program code and memory space in the interpolation routine by shifting values in the interpolation routine between shift registers and overwriting redundant data in ... | 04/06/1999 |
| 5805488 | Method and structure for degrouping MPEG audio codes An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. The decoder includes a deg... | 09/08/1998 |
