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| Number | Title | Issue Date |
| 7197526 | Method and apparatus for calculating the remainder of a modulo division A non-iterative technique for calculating the remainder of modulo division, which requires significantly fewer operations than the traditional iterative technique for the same calculation. The number of calculations required in the present invention is independent o... | 03/27/2007 |
| 7167889 | Decimal multiplication for superscaler processors A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partia... | 01/23/2007 |
| 6067617 | Specialized millicode instructions for packed decimal division A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequen... | 05/23/2000 |
| 5903485 | Division by a constant A ripple through divider of a dividend by a constant is obtained by cascading a plurality of partial quotient tables. Each table incorporates the same divisor, so the divisor need not appear as an input. In one binary integer implementation for an n bit d... | 05/11/1999 |
| 5715470 | Arithmetic apparatus for carrying out viterbi decoding at a high speed An arithmetic apparatus in which while data read out of a memory is shifted by means of a barrel shifter by a shift bit number designated by data standing for an output signal of an inverter, data standing for an output signal of the barrel shifter is inp... | 02/03/1998 |
| 5638314 | Dividing apparatus for use in a data processing apparatus A dividing apparatus which allows settlement of a quotient of one digit with a simple circuit construction is disclosed. A plurality of different integer multiples are simultaneously subtracted individually from a dividend or an intermediate remainder, an... | 06/10/1997 |
| 4817048 | Divider with quotient digit prediction A divider, which performs division in a base other than 2, that reduces in most cases the number of cycles it takes to generate each quotient digit. This involves predicting the minimum possible quotient digit in response to leading digits of the partial ... | 03/28/1989 |
| 4692891 | Coded decimal non-restoring divider This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division. A dividend is stored in a register B and a divis... | 09/08/1987 |
| 4635220 | Binary coded decimal number division apparatus A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted... | 01/06/1987 |
| 4603397 | Binary coded decimal number division apparatus In preparation of addresses of a quotient prediction table used in a binary coded decimal number division scheme with predetermined bits of a dividend and a divisor in binary coded decimal representation, the addresses are modified with the redundant bits... | 07/29/1986 |
| 4466077 | Method and apparatus for division employing associative memory A method and apparatus for the arithmetic division operation is disclosed in which a set of multiples of the divisor are stored in an associative memory in addresses which match the respective multiples. The most significant byte of the numerator is then ... | 08/14/1984 |
| 4384340 | Data processor having apparatus for controlling the selection of decimal digits of an operand when executing decimal arithmetic instructions A commercial instruction processor executes decimal arithmetic instructions on string decimal and packed decimal operands. A read only memory is responsive to control signals generated from the operation code portion of the instruction, a type signal from... | 05/17/1983 |
| 4384341 | Data processor having carry apparatus supporting a decimal divide operation A commercial instruction processor executes a decimal divide instruction by counting the number of subtractions by the divisor resulting in a positive remainder to develop the quotient. Apparatus compares the most significant decimal digit of the divisor ... | 05/17/1983 |
