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Pet Toilet-Like Water Disk and Food Storage
One pet-friendly inventor patented "a device for watering pets, e.g., a dog or cat." The device, he helpfully noted, "has the general shape of a toilet."
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| Number | Title | Issue Date |
| 7991818 | Division unit, image analysis unit and display apparatus using the same A division unit, an image analysis unit and a display apparatus using the same capable of simplifying the computation of overall average gray scale are provided. The division unit includes an adder for receiving a first to an Nth bus signals to produce an... | 08/02/2011 |
| 7747669 | Rounding of binary integers Methods and apparatus to provide rounding of a binary integer are described. In one embodiment, a value that indicates whether a divisor divides a binary integer is extracted from a product of the binary integer and a scaled approximate reciprocal of the divisor. | 06/29/2010 |
| 7702715 | Division arithmatic unit of variable radix A variable radix divider uses dividend, divisor and quotient as division operators and includes an adder/subtractor having inputs of the dividend and the divisor. The divider further includes a first and second quotient/radix generator having inputs of the dividend ... | 04/20/2010 |
| 7693929 | Hardware extension for accelerating fractional integer division within 3D graphics and MP3 applications An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of the invention a division operation is performed in no more than two cycles. In another embodiment of the... | 04/06/2010 |
| 7689642 | Efficient accuracy check for Newton-Raphson divide and square-root operations One embodiment of the present invention provides a system that efficiently performs an accuracy-check computation for Newton-Raphson divide and square-root operations. During operation, the system performs Newton-Raphson iterations followed by a multiply for the div... | 03/30/2010 |
| 7660842 | Method and apparatus for performing a carry-save division operation One embodiment of the present invention provides a system that performs a carry-save division operation that divides a numerator, N, by a denominator, D, to produce an approximation of the quotient, Q=N/D. The system approximates Q by iteratively selecting an operat... | 02/09/2010 |
| 7584237 | Fast hardware divider A method and mechanism for performing division. A processor includes a divider configured to perform arithmetic division operations. Prior to dividing a dividend by a divisor, the divider manipulates the dividend and divisor to reduce the number of bits considered a... | 09/01/2009 |
| 7567999 | Device and method for calculating a result of a division A device for calculating a result or an integer multiple of the result of a division of a numerator by a denominator includes a unit for providing a factor which is selected such that a product of the factor and the denominator is greater than the result. The device... | 07/28/2009 |
| 7523152 | Methods for supporting extended precision integer divide macroinstructions in a processor A method for an extended precision integer divide algorithm includes separating an L-bit integer dividend into two equal width integer format portions, a first portion including lower M bits of the integer dividend and a second portion including upper M bits of the ... | 04/21/2009 |
| 7487197 | Data processing apparatus incorporating a numeric processing mechanism A data processing apparatus uses numeric processing. A corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, always produce an accurate result but for which the ra... | 02/03/2009 |
| 7403966 | Hardware for performing an arithmetic function A circuit for performing an arithmetic function on a number performs the function using successive approximation. Each approximation produces an estimate of the result. A determination of the utility of this estimate is made by comparing the inverse function of a gi... | 07/22/2008 |
| 7395301 | Method and process for determining a quotient A method executed in a computing device for dividing by the integer number 48, the method includes receiving a number, and using the number in a combination of four additions and four bit-level shifts to produce a quotient representing the number divided by the inte... | 07/01/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7346644 | Devices and methods with programmable logic and digital signal processing regions A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly i... | 03/18/2008 |
| 7334012 | Reverse division process Described herein is a method that includes storing partial quotients of a continued fraction in a first set of counters, initializing a second sets of counters with counter values, decrementing a target counter in the second set of counters to obtain a decremented c... | 02/19/2008 |
| 7328358 | High quality and high performance three-dimensional graphics architecture for portable handheld devices A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be... | 02/05/2008 |
| 7313710 | High quality and high performance three-dimensional graphics architecture for portable handheld devices A high quality and performance 3D graphics architecture suitable for portable handheld devices is provided. The 3D graphics architecture incorporates a module to classify polygons by size and other characteristics. In general, small and well-behaved triangles can be... | 12/25/2007 |
| 7290025 | Calculation method for division of digital data, calculation apparatus for division of digital data, and program therefor A calculation speed of division carried out in a computer is increased. Partitioning means partitions a dividend y that is a 32-bit digital datum at every 8 bits from the least significant bit to generate four bit blocks y(1) to y(4). For the respectiv... | 10/30/2007 |
| 7277908 | Numeric processor, a numeric processing method, and a data processing apparatus or computer program incorporating a numeric processing mechanism Provided are methods, computer programs and data processing apparatus using numeric processing. Firstly, a corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, al... | 10/02/2007 |
| 7266150 | Interpolation of video compression frames A method, system, and computer programs for improving the image quality of one or more predicted frames in a video image compression system, where each frame comprises a plurality of pixels. A picture region or macroblock of certain types of frames can be encoded by... | 09/04/2007 |
| 7263624 | Methods and apparatus for power control in a scalable array of processor elements Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW util... | 08/28/2007 |
| 7251673 | Method for performing integer divisions A method of automatic calculation of several integer divisions by a same integer divider, of several successive integer dividends, separated from one another by a constant iteration step, smaller than or equal to the divider, including selecting, from a table of inc... | 07/31/2007 |
| 7243119 | Floating point computing unit A Sweeney Robertson Tocher (SRT) divider and a square root extractor of floating point double-precision bit width, including a selector of single-precision and double-precision, a carry propagation adder (CPA) for conducting carry propagation of a partial remainder,... | 07/10/2007 |
| 7230550 | Low-complexity bit-robust method and system for combining codewords to form a single codeword A system (100) and method (200) of combining codewords is provided. The system can include a splitter (120) for splitting a first codeword (110) into a most significant bits part MSP (112) and a least significant bits part LSP (... | 06/12/2007 |
| 7197526 | Method and apparatus for calculating the remainder of a modulo division A non-iterative technique for calculating the remainder of modulo division, which requires significantly fewer operations than the traditional iterative technique for the same calculation. The number of calculations required in the present invention is independent o... | 03/27/2007 |
| 7194075 | System and process for automatic storage, enforcement and override of consumer do-not-call requests A method of implementing call compliance at a central facility, the method involving: receiving a call from a caller on an incoming connection; enabling the caller on the incoming connection to initiate an outgoing call on an outgoing connection; receiving over the ... | 03/20/2007 |
| 7185040 | Apparatus and method for calculation of divisions and square roots Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {−1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial ... | 02/27/2007 |
| 7177421 | Authentication engine architecture and method Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in ... | 02/13/2007 |
| 7174357 | Circuitry for carrying out division and/or square root operations requiring a plurality of iterations Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, such as division or square root operations, utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives a... | 02/06/2007 |
| 7167891 | Narrow data path for very high radix division Methods, machines, and systems are provided for very high radix division using narrow data paths. A numerator and denominator are received for a very high radix division calculation. An approximate reciprocal of the denominator is obtained from a data structure. The... | 01/23/2007 |
| 7167887 | Circuitry for carrying out square root and division operations The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division opera... | 01/23/2007 |
| 7139786 | Method and apparatus for efficiently performing a square root operation One embodiment of the present invention provides a system that performs a carry-save square root operation that calculates an approximation of a square root, Q, of a radicand, R. The system calculates Q by iteratively selecting an operation to perform based on highe... | 11/21/2006 |
| 7130876 | Systems and methods for efficient quantization A method in a signal processor for quantizing a digital signal is provided. A fixed-point approximation of a value X÷Q is generated, wherein X is a fixed-point value based on one or more samples in the digital signal, and wherein Q is a fixed-point quantization par... | 10/31/2006 |
| 7127483 | Method and system of a microprocessor subtraction-division floating point divider The specification discloses a structure of and a method of operating a subtractive division (SD) cell where a portion of the partial remainder or estimated partial remainder directly indicates the next quotient digit. More particularly, by sufficiently constraining ... | 10/24/2006 |
| 7124160 | Processing architecture having parallel arithmetic capability According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operand... | 10/17/2006 |
| 7123033 | Method and an apparatus to detect low voltage A method and an apparatus to detect low voltage have been disclosed. One embodiment of the apparatus includes a main circuit powered at a supply voltage, wherein the supply voltage changes over time and a test circuit coupled to the main circuit, the test circuit be... | 10/17/2006 |
| 7119576 | Devices and methods with programmable logic and digital signal processing regions A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly i... | 10/10/2006 |
| 7079650 | Computing method for elliptic curve cryptography A fast cryptographic method between two entities exchanging data via a non-secure communication channel. The method, for example, forms a common key between two entities (A,B), each having a secret key (a,b) and using a public key (P) formed by a point of an ellipti... | 07/18/2006 |
| 7068785 | Table driven method for calculating arithmetic inverse for use in cryptography A method for calculating the arithmetic inverse of a number V modulo U, where U is a prime number, that may be used in cryptography, uses a modified extended greatest common divisor (GCD) algorithm that includes a plurality of reduction steps and a plurality of inve... | 06/27/2006 |
| 7065546 | Method of performing quantization within a multimedia bitstream utilizing division-free instructions Methods for enhancing the performance of quantization operations by converting division operations to a combination of multiplication and shift operations, which are preferably performed on a processor supporting single-instruction multiple-data (SIMD) instructions.... | 06/20/2006 |
