Bizarre Patents
Pneumatic Shoe Lacing Apparatus
This invention provides a pneumatic shoe lacing apparatus for the pneumatic lacing of shoe.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7707237 | Macrocell and method for adding A macrocell including an adder block with a plurality of bit-slice adders, a bypass path and a control unit adapted to receive a carry of a first neighboring macrocell, and to output a carry by generation within the adder block or by passage of the carry of the firs... | 04/27/2010 |
| 7627625 | Long-integer multiplier An adder circuit for multiplying two long integers deploys a network of adders for summing a succession of words of the long integers to generate intermediate results. The number of addends varies as a function of bit position and the network of adders is designed t... | 12/01/2009 |
| 7334200 | Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. ... | 02/19/2008 |
| 7296049 | Fast multiplication circuits Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier. Generation of a final product is made faster because fewer interstitial pr... | 11/13/2007 |
| 7272624 | Fused booth encoder multiplexer A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results... | 09/18/2007 |
| 7269616 | Transitive processing unit for performing complex operations The present invention provides a circuit for a programmable transitive processing unit for performing complex functions, such as multiplication, pipelining of one or more values, and/or shift operations, wherein the circuit can be configured to be a constituent of a... | 09/11/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7225217 | Low-power Booth-encoded array multiplier An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does no... | 05/29/2007 |
| 7206801 | Digital multiplier with reduced spurious switching by means of Latch Adders A digital Parallel Multiplier has a Partial Product Generator, a First Stage Adder Circuit and a Final Stage Adder Circuit. The spurious switching in the First Stage Adder Circuit may be substantially reduced by synchronizing the input signals to the Adders in First... | 04/17/2007 |
| 7139787 | Multiply execution unit for performing integer and XOR multiplication A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The partial products may be Booth e... | 11/21/2006 |
| 7096246 | Arithmetic unit for multiplying a first quantity X by a second quantity Y An arithmetic unit for multiplying a first quantity x by a second quantity y, the arithmetic unit including a Booth coder having a plurality of inputs for receiving a plurality bits of the second quantity and a plurality of outputs for providing Booth coded outputs;... | 08/22/2006 |
| 7043520 | High-speed/low power finite impulse response filter A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response f... | 05/09/2006 |
| 7024445 | Method and apparatus for use in booth-encoded multiplication A new partial product bit generator is used to generate a partial product bit PPji. In some embodiments, the partial product bit generator generates the partial product bit PPji from intermediate signals that are able to be generated concurrent... | 04/04/2006 |
| 6978426 | Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. ... | 12/20/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6901423 | Noise invariant circuits, systems and methods The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip o... | 05/31/2005 |
| 6804354 | Cryptographic isolator using multiplication A stream cipher cryptosystem includes a pseudo-random bit generator receiving a key and providing a vulnerable keystream vulnerable to crytanalysis, and a non-linear filter cryptographic isolator to convert the vulnerable keystream into a protected keystream. The no... | 10/12/2004 |
| 6763367 | Pre-reduction technique within a multiplier/accumulator architecture An apparatus and method for compressing a reduction array into an accumulated carry-save sum. The reduction array includes a partial product matrix, a carry-save sum, and a constant value row. A compressor array generates a previous accumulated carry-save sum. A thr... | 07/13/2004 |
| 6704762 | Multiplier and arithmetic unit for calculating sum of product In a case of performing a multiplication operation with low accuracy, a value of the most significant bit included in the least significant half the bits of a multiplier is replaced with "0". A Booth decoder divides the multiplier into a plurality of part... | 03/09/2004 |
| 6704761 | Carry-save multiplier/accumulator system and method A method is described for providing an improved multiplier/accumulator which utilizes less processing resources than such devices which are known in the prior art. The methodology operates to utilize the processing resources of a multiplier-accumulator co... | 03/09/2004 |
| 6567834 | Implementation of multipliers in programmable arrays Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided ... | 05/20/2003 |
| 6473529 | Sum-of-absolute-difference calculator for motion estimation using inversion and carry compensation with full and half-adders A specialized Sum-of-Absolute-Difference (SAD) calculator for motion estimation uses inversion rather than 2's complementing. The absolute-value operation of each pixel-pair difference is performed by a bit-wise inversion rather than a complement. This re... | 10/29/2002 |
| 6421699 | Method and system for a speedup of a bit multiplier A method and system is provided which overlaps the process of partial product reduction and the final adder in both higher- and lower-order bits when performing multiplication. The method and system reduces the number of left-over bits such that the final... | 07/16/2002 |
| 6393454 | Booth multiplier with low power, high performance input circuitry A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplie... | 05/21/2002 |
| 6272513 | Multiplying device A multiplying device operates for implementing multiplication between multiplicand data and multiplier data in a two's complement representation form. Each of the multiplicand data and the multiplier data has n bits, where n denotes a predetermined even n... | 08/07/2001 |
| 6249799 | Selective carry boundary An adder tree includes several partial product generators, each generating a bit of equal weight. An adder receives the bits and provides a carry bit to a logic unit. The logic unit propagates the carry bit to the next more significant column in response ... | 06/19/2001 |
| 6240438 | Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability A multiplier circuit has an encoder and a partial product bit generating circuit. The encoder receives a multiplier bit signal and is used to output a plurality of encode signals. The partial product bit generating circuit receives the encode signals alon... | 05/29/2001 |
| 6173304 | Joint optimization of modified-booth encoder and partial product generator A multiplier contains an array of partial product generators, at least one new modified-Booth encoder. Corresponding to each new modified-Booth encoder, the partial product generator array includes a new adder cell. The partial product generator array rec... | 01/09/2001 |
| 6131107 | Fast determination of carry inputs from lower order product for radis-8 odd/even multiplier array A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes lo... | 10/10/2000 |
| 6029187 | Fast regular multiplier architecture A multiplier architecture in accordance with the present invention provides increased operating speed, and yet maintains regularity in its structure in order to achieve a small floor plan when reduced to silicon. A Hekstra-type multiplier is modified by r... | 02/22/2000 |
| 6021424 | Booth multiplier with low power, high performance input circuitry A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplie... | 02/01/2000 |
| 6004022 | Product sum operation apparatus A product sum operation apparatus in which an increase in the circuit scale of the product sum operation apparatus can be suppressed and the operation speed can be increased even when the number of bits to be operated is increased. A partial product gener... | 12/21/1999 |
| 5974437 | Fast array multiplier A number of adder structures (also referred to herein as "tiles" and "Quickadders™") are provided which may be constructed with positively and/or negatively weighted and signed inputs and outputs and which may be placed so as to span one or more bitslic... | 10/26/1999 |
| 5953241 | Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a... | 09/14/1999 |
| 5935202 | Compressor circuit in a data processor and method therefor A multiplier in a data processing system has a modified compressor structure which is configured to alleviate both a tendency of the multiplier to be wire bound and to optimize a circuit area required to implement the multiplier. In the modified compresso... | 08/10/1999 |
| 5909385 | Multiplying method and apparatus A multiplying apparatus includes a Booth decoder for performing a second-order Booth decode on a multiplier, a Booth selector for generating a partial product except the two high-order digits from the output of the decoder and a multiplicand, a partial pr... | 06/01/1999 |
| 5889692 | Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes lo... | 03/30/1999 |
| 5889691 | Apparatus and method for a multiplier unit with high component utilization In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multip... | 03/30/1999 |
| 5867415 | Multiplication element including a wallace tree circuit having adders divided into high and low order adders A multiplication element including a plurality of partial product generating circuits for inputting a multiplicand and a plurality of modified multipliers obtained based on a multiplier, and for generating 0th partial products corresponding to ... | 02/02/1999 |
| 5841674 | Circuit design methods and tools A circuit design tool which includes an architecture for a multiplier which is faster and more compact than known multipliers through the use of Wallace trees, the elimination of Dadda nodes along the critical paths, the placement of half-adders at an ini... | 11/24/1998 |
