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| Number | Title | Issue Date |
| 8099450 | Multiplication circuitry Combining circuitry for combining a plurality of multi-bit partial product terms in a multiplier circuit includes a plurality of compression columns, each column receiving a plurality of partial product term bits. At least one compression column includes: a first ci... | 01/17/2012 |
| 7424506 | Architecture and related methods for efficiently performing complex arithmetic A method is presented comprising analyzing two or more input terms on a per-bit basis within each level of bit-significance. Maximally segmenting each of the levels of bit-significance into one or more one-, two-, and/or three-bit groups, and designing a hyperpipeli... | 09/09/2008 |
| 7392277 | Cascaded domino four-to-two reducer circuit and method A cascaded differential domino four-to-two reducer. In an embodiment, the four-to-two reducer is constructed of a first three-to-two reducer and a second three-to-two reducer directly connected to the first three-to-two reducer. In a further embodiment, the first an... | 06/24/2008 |
| 7373368 | Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication A multiply execution unit that can generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier. The multiply execution unit includes a summing circuit for summing a plurality... | 05/13/2008 |
| 7334200 | Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. ... | 02/19/2008 |
| 7330869 | Hybrid arithmetic logic unit Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: ... | 02/12/2008 |
| 7315879 | Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110... | 01/01/2008 |
| 7313585 | Multiplier circuit A multiplier circuit is disclosed for multiplying a multiplicand by a multiplier. The multiplier circuit includes a partial product generator and a partial product adder. The partial product generator includes a first input to receive a multiplicand; a second input ... | 12/25/2007 |
| 7251581 | Circuit for computing moment pre-products for statistical analysis A circuit for computing moment pre-products for statistical analysis reduces data transfer volume for on-chip statistical measurements. The circuit calculates the sums of multiple exponentiations of outputs of one or more measurement circuits, thereby reducing the a... | 07/31/2007 |
| 7236999 | Methods and systems for computing the quotient of floating-point intervals Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and... | 06/26/2007 |
| 7225217 | Low-power Booth-encoded array multiplier An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does no... | 05/29/2007 |
| 7219117 | Methods and systems for computing floating-point intervals Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first ... | 05/15/2007 |
| 7212959 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 05/01/2007 |
| 7124162 | Adder tree structure digital signal processor system and method A Wallace tree structure such as that used in a digital signal processor (DSP) is arranged to sum vectors. The structure has a number of adder stages, each of which may have half adders with two input nodes, and full adders with three input nodes. The structure is d... | 10/17/2006 |
| 7111166 | Extending the range of computational fields of integers An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field,... | 09/19/2006 |
| 7111033 | Carry save adders A carry save adder circuit for reducing the number of inputs to a lower number of outputs, the carry save adder circuit including four carry save adders, the four carry save adders being arranged in two layers with the first and second carry save adders being arrang... | 09/19/2006 |
| 7085797 | Addition circuit for accumulating redundant binary numbers An addition circuit for producing a sum of four redundant binary numbers includes a 4:2 compression adder for receiving each of the operand fields of the four redundant binary numbers, and producing a first sum field and a first carry field therefrom. The addition c... | 08/01/2006 |
| 7043520 | High-speed/low power finite impulse response filter A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response f... | 05/09/2006 |
| 7039667 | 4-2 compressor A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a f... | 05/02/2006 |
| 7035893 | 4-2 Compressor A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a f... | 04/25/2006 |
| 7007053 | Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output An area-efficient realization of a coefficient block includes hardware sharing techniques and optimizations applied to this block. The block is connected to coefficient lines coming from a delay block to be connected to perform a filtering operation or a mathematica... | 02/28/2006 |
| 6993071 | Low-cost high-speed multiplier/accumulator unit for decision feedback equalizers A multiplier device for multiplying one of a discrete set of digital level values with a filter coefficient in a filter device implemented in a decision feedback equalizer including (i) a decoder device for receiving a discrete digital level value to be multiplied a... | 01/31/2006 |
| 6989843 | Graphics system with an improved filtering adder tree A sample-to-pixel calculation unit in a graphics system may comprise an adder tree. The adder tree includes a plurality of adder cells coupled in a tree configuration. Input values are presented to a first layer of adder cells. Each input value may have two associat... | 01/24/2006 |
| 6978426 | Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. ... | 12/20/2005 |
| 6973471 | Method and apparatus for implementing signed multiplication of operands having differing bit widths without sign extension of the multiplicand A multiplier (42) forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun immediately without being delayed by a sign extension operation. While r... | 12/06/2005 |
| 6938061 | Parallel counter and a multiplication logic circuit A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary... | 08/30/2005 |
| 6925480 | Microarchitecture of an arithmetic unit The microarchitecture of the arithmetic unit includes two cascaded N bit adders to provide an N bits result in an accumulator. The arithmetic unit also includes a carry save adder, followed by an adder, which, along with the accumulator, are extended to N+1 bits. A ... | 08/02/2005 |
| 6904447 | High speed low power 4-2 compressor A high speed low powered 4-2 compressor according to the present invention performs an XOR/XNOR operation of input data by using a single input type NAND/NOR logic circuit and a dual input type NAND/NOR logic circuit. Thus, delays to generate complementary signals a... | 06/07/2005 |
| 6763367 | Pre-reduction technique within a multiplier/accumulator architecture An apparatus and method for compressing a reduction array into an accumulated carry-save sum. The reduction array includes a partial product matrix, a carry-save sum, and a constant value row. A compressor array generates a previous accumulated carry-save sum. A thr... | 07/13/2004 |
| 6732135 | Method and apparatus for accumulating partial quotients in a digital processor In a digital processor performing division, quotient accumulation apparatus is formed of a set of muxes and a single carry save adder. Partial quotients are accumulated in carry-save form with proper sign extension. Delay of partial quotient bit fragments from one i... | 05/04/2004 |
| 6721774 | Low power multiplier A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results sign... | 04/13/2004 |
| 6692534 | Specialized booth decoding apparatus The present invention provides an apparatus for booth decoding which stores the most significant bit of the lower half of the number used as the key for booth decoding. By using this stored bit to determine the rightmost booth group corresponding to the u... | 02/17/2004 |
| 6615229 | Dual threshold voltage complementary pass-transistor logic implementation of a low-power, partitioned multiplier The present invention relates to a new low-power, high performance multiplier circuit design, and more specifically to a partitioned multiplier implemented using a modified, symmetrical Wallace tree structure that enables the power to parts of the multipl... | 09/02/2003 |
| 6611857 | Method and system for reducing power in a parallel-architecture multiplier A multiplier (12) is disclosed that includes an encoder (36), a hierarchy of compressors (40, 42, 44, 50, 52, 60 and 70), a bit detector (130) and a switch (134). The encoder (36) is operable to receive a first and second encoder input. The compressors (4... | 08/26/2003 |
| 6535902 | Multiplier circuit for reducing the number of necessary elements without sacrificing high speed capability A multiplier circuit has an encoder and a partial product bit generating circuit. The encoder receives a multiplier bit signal arid is used to output a plurality of encode signals. The partial product bit generating circuit receives the encode signals alo... | 03/18/2003 |
| 6535901 | Method and apparatus for generating a fast multiply accumulator A method and apparatus for generating a fast multiply accumulation circuit includes processing that begins by determining number of current partial products for a multiplication of a first multiplicand and a second multiplicand. The processing then contin... | 03/18/2003 |
| 6484193 | Fully pipelined parallel multiplier with a fast clock cycle A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a... | 11/19/2002 |
| 6460064 | Multiplier for operating n bits and n/2 bits and method therefor A multiplier for multiplying n bits and n/2 bits is disclosed, wherein a word multiplication is implemented by input of two words. The apparatus includes an encoder receiving the two words and pretreating one of the two words, a partial product generating... | 10/01/2002 |
| 6446104 | Double precision floating point multiplier having a 32-bit booth-encoded array multiplier A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and sum... | 09/03/2002 |
| 6442582 | Multiplier carry bit compression apparatus and method A multiplier carry bit compression apparatus and method for a multiplier using Wallace tree addition structures uses a plurality of early and late carry bit compression operations for each level of the Wallace tree addition structure. For each level in a ... | 08/27/2002 |
