Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 8112468 | Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC Some embodiments provide a method of performing a mathematical operation on a set of operands. The mathematical operation includes several sub-operations. The method examines several bits of at least one operand at a time and depending on the value of these bits, re... | 02/07/2012 |
| 7930337 | Multiplying two numbers Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B. | 04/19/2011 |
| 7912891 | High speed low power fixed-point multiplier and method thereof Provided are a high speed and low power fixed-point multiplier and method thereof. The multiplier includes: a partial product calculation unit for dividing input data into a plurality of bit groups, each bit group having a predetermined number of bits, generating pa... | 03/22/2011 |
| 7895255 | Method and apparatus for performing a multiplication or division operation in an electronic circuit A multiplication or division operation X·K or X·1/K is performed in an electronic circuit. A software circuit area of the circuit calculates a digit shift sv such that psv is an approximate value for K. In a hardware circuit area, the value X is shifted... | 02/22/2011 |
| 7856467 | Integrated circuit including at least one configurable logic cell capable of multiplication The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said... | 12/21/2010 |
| 7840628 | Combining circuitry A combining circuit and method combines a plurality of terms in a multiplier circuit. The combining circuit includes a first circuit, arranged to receive a first set of the plurality of terms and to combine the first set of terms to produce a first combined term set... | 11/23/2010 |
| 7818361 | Method and apparatus for performing two's complement multiplication Some embodiments provide a novel way of performing a signed multiplication. Each individual bit of a first operand is multiplied by every bit of a second operand to generate partial multiplication results. Each partial result is shiftably added to other partial resu... | 10/19/2010 |
| 7797365 | Design structure for a booth decoder A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circ... | 09/14/2010 |
| 7797364 | Booth decoder apparatus and method A Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal outpu... | 09/14/2010 |
| 7769797 | Apparatus and method of multiplication using a plurality of identical partial multiplication modules A multiplication apparatus including a multiplier and multiplicand extractor for dividing the multiplicand into partial multiplicands and dividing the multiplier into partial multipliers, and for generating partial input pairs by combining the partial multiplicands ... | 08/03/2010 |
| 7725522 | High-speed integer multiplier unit handling signed and unsigned operands and occupying a small area A high-speed integer multiplier unit multiplying operands, wherein each operand can be either signed or unsigned. Type data is received for each operand which indicates whether the corresponding operand is to be treated as signed or unsigned. An extend bit is append... | 05/25/2010 |
| 7685222 | Power of two multiplication engine A multiplication engine is described in which a decision threshold engine utilizes a Y-adder powers of two shift table to iteratively generate shift-add combinations. The shift-add combinations are output in a sequence with decreasing levels of contribution wherein ... | 03/23/2010 |
| 7672989 | Large number multiplication method and device A signed multiplication method and a corresponding device for multiplying a first multiplicand with a second multiplicand. The device stores the first multiplicand in a first register as a first vector of at least one respective digit and storing the second multipli... | 03/02/2010 |
| 7599981 | Binary polynomial multiplier A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations. To this end, the multiply unit may include an input data path that receives input operands, an arithmetic multiplier connected to receive the input operands, ... | 10/06/2009 |
| 7587443 | Digital signal processor with efficient multi-modal multiplier A digital signal processor architecture allows the digital signal processor to be used efficiently for multiplying words which are longer than the word length for which the architecture is primarily designed. The multiplication unit has a register file which is adap... | 09/08/2009 |
| 7567998 | Method and system for multiplier optimization Described herein is a method and system for multiplier optimization. A gate count savings that does not introduce additional quantization error can be achieved with this method and system. By increasing the number of digits in a multiplication result, partial produc... | 07/28/2009 |
| 7565391 | Binary digit multiplications and applications A multiplying system for binary digits. The digits are multiplied in a rectangular memory array, where the digits are placed along the edges, and intersections between 1's form blocks of 1's in the memory array. The blocks of 1's are evaluated based on a weighting a... | 07/21/2009 |
| 7490121 | Modular binary multiplier for signed and unsigned operands of variable widths A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier s... | 02/10/2009 |
| 7447726 | Polynomial and integer multiplication A method and apparatus for generating a plurality of concurrent significant bits forming at least a portion of a product from at least two partial products, the method comprising the following steps: for each of a plurality of said concurrent predetermined significa... | 11/04/2008 |
| 7401109 | Multiplication of multi-precision numbers having a size of a power of two Multi-precision multiplication methods include storing a first operand and a second operand as a first array and a second array of n words. A first weighted sum is determined from multiple subproducts of corresponding words of the first operand and the second operan... | 07/15/2008 |
| 7392276 | Efficient multiplication sequence for large integer operands wider than the multiplier hardware A method of operating a multiplication circuit to perform multiply-accumulate operations on multi-word operands is characterized by an operations sequencer that is programmed to direct the transfer of operand segments between RAM and internal data registers in a spe... | 06/24/2008 |
| 7389317 | Long instruction word controlling plural independent processor operations A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a s... | 06/17/2008 |
| 7373368 | Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication A multiply execution unit that can generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier. The multiply execution unit includes a summing circuit for summing a plurality... | 05/13/2008 |
| 7370082 | Remote invalidation of pre-shared RDMA key Methods, systems, and computer program products for reducing communication overhead to make remote direct memory access more efficient for smaller data transfers. An upper layer protocol or other software creates a receive buffer and a corresponding lookup key for r... | 05/06/2008 |
| 7366746 | Finite impulse response filter method and apparatus Finite response filters (FIRs) are divided into partial filters that filter a same portion of image data to generate partial filtered results. The partial filtered results may be saved and later retrieved to generate complete filter outputs. ... | 04/29/2008 |
| 7356554 | Variable fixed multipliers using memory blocks A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the... | 04/08/2008 |
| 7346644 | Devices and methods with programmable logic and digital signal processing regions A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly i... | 03/18/2008 |
| 7328230 | SIMD four-data element average instruction According to some embodiments, a Single-Instruction/Multiple-Data averaging operation is presented. The averaging operation averages multiple sets of data elements, for example, two data elements each from a first source and a second source, producing a set of avera... | 02/05/2008 |
| 7321321 | Decoding of a restricted m-of-n code A method for communication between a sender and a receiver, including receiving data in the form of an M-of-N code, where the M-of-N code includes a first component of length n1 and a second component of length n2; decoding data in which the fi... | 01/22/2008 |
| 7318080 | Split radix multiplication A first number is multiplied by a second number, by representing the first number as a first set of one or more W-bit wide numbers, and representing the second number as a second set of one or more W-bit wide numbers. Each of the W-bit wide numbers from the first se... | 01/08/2008 |
| 7315163 | Arithmetic unit In order to correct an overflow of a multiplication result while improving the operation speed, an overflow detection unit detects an overflow based on whether a multiplicand A and a multiplier B are both a negative value with the largest absolute value. A carry-sav... | 01/01/2008 |
| 7315879 | Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110... | 01/01/2008 |
| 7301933 | Delivery of a service program to a digital signal processor within a multiservice processing system A method including determining whether a digital signal processor needs a service program stored in a juke box overlay memory, and delivering the service program to the digital signal processor from the juke box overlay memory over a host port interface bus is discl... | 11/27/2007 |
| 7296049 | Fast multiplication circuits Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier. Generation of a final product is made faster because fewer interstitial pr... | 11/13/2007 |
| 7284029 | 4-to-2 carry save adder using limited switching dynamic logic A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry s... | 10/16/2007 |
| 7277540 | Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit... | 10/02/2007 |
| 7275076 | Multiplication logic circuit A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length col... | 09/25/2007 |
| 7269617 | Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers embedded in DSP circuitry integrated in the PLD. A smaller DSP multiplier ... | 09/11/2007 |
| 7269616 | Transitive processing unit for performing complex operations The present invention provides a circuit for a programmable transitive processing unit for performing complex functions, such as multiplication, pipelining of one or more values, and/or shift operations, wherein the circuit can be configured to be a constituent of a... | 09/11/2007 |
| 7266580 | Modular binary multiplier for signed and unsigned operands of variable widths A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-ful... | 09/04/2007 |
