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| Number | Title | Issue Date |
| 7194498 | Higher radix multiplier with simplified partial product generator A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a digital processor. ... | 03/20/2007 |
| 7167889 | Decimal multiplication for superscaler processors A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partia... | 01/23/2007 |
| 5499299 | Modular arithmetic operation system A modular arithmetic unit comprises an input register, a multiple computing section, an adder, and a correcting section. There is provided a multiple table in which multiples of a modulo N are stored to correspond with low-order some bits of an input numb... | 03/12/1996 |
| 5379245 | Decimal multiplying assembly and multiply module A modular multiplying assembly and a multiply module for use in the multiplying assembly implemented by hard-wired circuits are disclosed. Each module calculates multiplication for operands of a decimal single digit and can receive a carry or carries from... | 01/03/1995 |
| 5258945 | Method and apparatus for generating multiples of BCD number The times-two (×2) through times-nine (×9) multiples of a supplied multi-digit BCD number are produced using one machine cycle for performing a set-up operation and thereafter one additional machine cycle for producing all the ×2-×9 multiples. A multi... | 11/02/1993 |
| 4677583 | Apparatus for decimal multiplication An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and a... | 06/30/1987 |
| 4615016 | Apparatus for performing simplified decimal multiplication by stripping leading zeroes Processor apparatus is described for performing binary and decimal arithmetic operations. In performing decimal multiplication with the processor apparatus, to reduce the amount of processing to be done with the apparatus and thereby speed up the performa... | 09/30/1986 |
| 4566075 | Table lookup multiplier employing compressed data read only memory A multiplier circuit including a read-only memory containing a table of products for digits of a multiplicand and multiplier. The multiplier circuit will produce the product when a multiplicand digit and a multiplier digit are input. The contents of the m... | 01/21/1986 |
| 4543641 | Multiplication device using multiple-input adder A multiplier device comprising hold means for holding the result of addition, block product means for producing k block products each having 2n bits, where n is an integer equal to or greater than 2, the k block products being formed by multiplying each b... | 09/24/1985 |
| 4484300 | Data processor having units carry and tens carry apparatus supporting a decimal multiply operation A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decima... | 11/20/1984 |
| 4390961 | Data processor performing a decimal multiply operation using a read only memory A data processor performs a decimal multiply operation using apparatus including a register for storing multiplier decimal digits, a register for storing a multiplicand operand of decimal digits, a register for storing partial products and arithmetic logi... | 06/28/1983 |
| 4384340 | Data processor having apparatus for controlling the selection of decimal digits of an operand when executing decimal arithmetic instructions A commercial instruction processor executes decimal arithmetic instructions on string decimal and packed decimal operands. A read only memory is responsive to control signals generated from the operation code portion of the instruction, a type signal from... | 05/17/1983 |
