Bizarre Patents
A hand wearable body squeegee comprising a glove portion, a concave squeegee band, and a linear squeegee band.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7680873 | Methods and apparatus for efficient complex long multiplication and covariance matrix implementation Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communicati... | 03/16/2010 |
| RE40803 | Complex number multiplier The invention concerns a complex number multiplier receiving the binary number A, B, C and D complimentarily coded in pairs so as to perform the complex multiplication (A+jB)*(C+jD). A first processing stage enables to perform the operations A−B, C−D, and A+B wh... | 06/23/2009 |
| 7546329 | Systems for performing multiplication operations on operands representing complex numbers A method for multiplying, at an execution unit of a processor, two complex numbers in which all four scalar multiplications, concomitant to multiplying two complex numbers, can be performed in parallel. A real part of a first complex number is multiplied at the exec... | 06/09/2009 |
| 7546330 | Systems for performing multiply-accumulate operations on operands representing complex numbers A method for multiplying, at an execution unit of a processor, two complex numbers in which a real part and an imaginary part of a product of the multiplying can be stored in a same register of the processor. First data is conveyed along at least a first interconnec... | 06/09/2009 |
| 7424506 | Architecture and related methods for efficiently performing complex arithmetic A method is presented comprising analyzing two or more input terms on a per-bit basis within each level of bit-significance. Maximally segmenting each of the levels of bit-significance into one or more one-, two-, and/or three-bit groups, and designing a hyperpipeli... | 09/09/2008 |
| 7415542 | Micro-programmable filter engine having plurality of filter elements interconnected in chain configuration wherein engine supports multiple filters from filter elements A micro-programmable filter (MFE) engine includes multiple programmable filter elements and a microcode controller. The filter elements can be configured, controlled, and combined in different ways to implement different types of filters. The MFE preferably supports... | 08/19/2008 |
| 7339503 | Adaptive asynchronous sample rate conversion A system including a buffer, a feedback loop configured to generate a fractional delay from a ratio of a first number of samples written into the buffer to a second number of samples read from the buffer, and a variable fractional delay filter configured to generate... | 03/04/2008 |
| 7333530 | Despread signal recovery in digital signal processors A digital signal processor performs despread decoding in wireless telephone systems. Orthogonal codes are used to combine data signals into one overall coded signal which is transmitted. The orthogonal codes are used to retrieve individual data signals from the tran... | 02/19/2008 |
| 7327783 | Frequency translator using a cordic phase rotator A frequency translator uses a CORDIC phase rotator coupled to a phase accumulator to translate an input signal in frequency. The CORDIC phase rotator performs required phase angle rotations of input vectors using only shift and add operations. Thus, the frequency tr... | 02/05/2008 |
| 7313166 | Multicode receiver A code division multiple access (CDMA) receiver detects, de-scrambles, and de-spreads multiple channels that utilize different binary codes. The processing that is common to all channels can be performed once thus saving gate count and power consumption. ... | 12/25/2007 |
| 7287051 | Multi-functional digital signal processing circuitry Multi-functional digital signal processing (“DSP”) circuitry can perform any of a wide range of different DSP functions. For example, the DSP circuitry can perform multiplication of simple or complex numbers of different lengths. The multiplication of simple (i.... | 10/23/2007 |
| 7284027 | Method and apparatus for high speed calculation of non-linear functions and networks using non-linear function calculations for digital signal processing The invention includes apparatus and methods for high-speed calculation of non-linear functions based upon a shifted adder and a offset generator. Various implementations may preferably include a input preprocessor and/or an output post processor. The invention incl... | 10/16/2007 |
| 7216140 | Efficient implementation of n-point DCT, n-point IDCT, SA-DCT and SA-IDCT algorithms An efficient implementation of n-point discrete cosine transform, n-point inverse discrete cosine transform, shape adaptive discrete cosine transform and shape adaptive inverse discrete cosine transform algorithms for multimedia compression and decompression optimiz... | 05/08/2007 |
| 7203718 | Apparatus and method for angle rotation An angle rotator uses a coarse stage rotation and a fine stage rotation to rotate an input complex signal in the complex plane according to an angle θ. The coarse stage rotation includes a memory device storing pre-computed cosine θM and sine θM | 04/10/2007 |
| 7197089 | Frequency plan for GPS receiver The present invention provides a GPS receiver having a unique frequency plan, thereby eliminating interference due to internally generated frequencies. In general, the GPS receiver has downconversion circuitry that uses a first synthesizer output signal with a cente... | 03/27/2007 |
| 7174356 | Complex multiplication method and apparatus with phase rotation A method and apparatus for complex multiplication includes steps of: (a) receiving a complex multiplicand having a real value and an imaginary value (704); (b) generating a negation of the real value of the complex multiplicand (706); (c) generating a ... | 02/06/2007 |
| 7133040 | System and method for performing an insert-extract instruction An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements... | 11/07/2006 |
| 7113970 | Complex-valued multiplier-and-accumulator The multi-mode Multiplier-And-Accumulator of the present invention is used with the double-precision Complex-Valued Multiplier-And Accumulator as a main configuration, and the different precisions and digital modes make it more flexible, compared to the traditional ... | 09/26/2006 |
| 7099406 | Alias sampling for IF-to-baseband conversion in a GPS receiver The present invention provides a GPS receiver comprising sampling circuitry adapted to perform IF-to-baseband conversion. In general, the GPS receiver includes downconversion circuitry that uses a first synthesizer output signal to reduce an amplified GPS input sign... | 08/29/2006 |
| 7082451 | Reconfigurable vector-FFT/IFFT, vector-multiplier/divider Systems and methods are described for providing a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes The circuit may be controllably configures to perform a fast Fourier transform function, a multiplier fu... | 07/25/2006 |
| 7080183 | Reprogrammable apparatus supporting the processing of a digital signal stream and method An architecture is provided that includes a reconfigurable bridge for routing data among functional units. Register transfer units effect the routing of data among registers that are associated with each functional unit. Synchronous and asynchronous register transfe... | 07/18/2006 |
| 7076008 | Method and apparatus for estimating and correcting gain and phase imbalance in a code division multiple access system Gain and phase imbalance is estimated by using an IQ-swapped spreading sequence in addition to a regular spread pilot signal. The IQ-swapped spreading sequence is the spreading sequence whose real and imaginary components are the imaginary and real components of the... | 07/11/2006 |
| 7072929 | Methods and apparatus for efficient complex long multiplication and covariance matrix implementation A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The m... | 07/04/2006 |
| 7069372 | Processor having systolic array pipeline for processing data packets A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of progr... | 06/27/2006 |
| 7065629 | Address translation logic for use in a GPS receiver The address translation logic of the present invention is incorporated in a global positioning system (GPS) receiver and operates to group data in memory based on translating the address from a direct memory access controller. The data includes post-correlated sampl... | 06/20/2006 |
| 7062637 | DSP operations with permutation of vector complex data type operands Executing digital signal processing (DSP) instructions in a digital signal processor integrated circuit comprising receiving a DSP instruction in digital signal processor integrated circuit to process one or more complex number operands; fetching a first operand wit... | 06/13/2006 |
| 7051061 | Dual use dual complex multiplier and complex divider A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth c... | 05/23/2006 |
| 7051263 | Systolic architecture for Comma-Free Reed-Solomon decoding circuit A Comma-Free Reed-Solomon decoding circuit based on systolic array architecture that applies to a cell search in a wideband code division multiple access system, and more particularly a decoding circuit that employs a systolic array in its circuit structure. The sys... | 05/23/2006 |
| 7050999 | System for computing probability distribution of loan losses A system for computing probability distribution of loan losses includes a loan amount and bankruptcy probability input device for inputting loan amounts and bankruptcy probabilities of individual loan customers, a characteristic function calculating device for calcu... | 05/23/2006 |
| 7047269 | Cordic method and architecture applied in vector rotation A CORDIC method and a CORDIC architecture applied in vector rotation are disclosed. An elementary angles set is extended by representing the elementary angles as the arctangent of the sum of two single signed-power-of-two terms to an extended elementary angles set. ... | 05/16/2006 |
| 7020190 | Frequency translator using a cordic phase rotator A frequency translator uses a CORDIC phase rotator coupled to a phase accumulator to translate an input signal in frequency. The CORDIC phase rotator performs required phase angle rotations of input vectors using only shift and add operations. Thus, the frequency tr... | 03/28/2006 |
| 7017104 | Method and system for decoding block codes by calculating a path metric according to a decision feedback sequence estimation algorithm A method and system are disclosed that provide a more efficient decoder for decoding block codes such as a complementary code keying (CCK) code. A receiver receives a signal containing at least one block codeword. A decoder decodes the block codeword contained in th... | 03/21/2006 |
| 7013321 | Methods and apparatus for performing parallel integer multiply accumulate operations According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. ... | 03/14/2006 |
| 7010558 | Data processor with enhanced instruction execution and method An apparatus and method for performing enhanced algorithmic processing, including reduced cycle-count fast Fourier transform (FFT) calculations. In one aspect, the invention comprises a user-configurable processor having an extension instruction adapted for reduced ... | 03/07/2006 |
| 6999985 | Single instruction multiple data processing A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in respo... | 02/14/2006 |
| 6976047 | Skipped carry incrementer for FFT address generation A method and apparatus are used to generate FFT data addresses for a butterfly stage based upon a computation stage value. The method includes setting a selected bit of a binary word at a logical value, performing an addition operation by adding a logical “1” to... | 12/13/2005 |
| 6970994 | Executing partial-width packed data instructions A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectur... | 11/29/2005 |
| 6944813 | Weighted decoding method and circuits for Comma-Free Reed-Solomon codes A weighted decoding method and circuits for Comma-Free Reed-Solomon codes that apply to a cell search in a wideband code division multiple access system. The invention also provides a weighted decoding method wherein the decoding result of the secondary synchronizat... | 09/13/2005 |
| 6928600 | Folding systolic architecture for comma-free reed-solomon decoding circuit A kind of folding systolic array architecture for a CFRS decoding circuit that applies to a cell search in a wideband code division multiple access system. The invention involves using a systolic array for its decoding circuit and using a kind of folding technology ... | 08/09/2005 |
| 6925553 | Staggering execution of a single packed data instruction using the same circuit A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, ... | 08/02/2005 |
