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| Number | Title | Issue Date |
| 8082287 | Pre-saturating fixed-point multiplier A pre-saturating multiplier inspects the operands to a multiply operation prior to performing any multiplication. If the operands will cause an overflow requiring saturation, the multiplier outputs the saturated value without multiplying the original operands. In on... | 12/20/2011 |
| 8046401 | Canonical signed digit multiplier A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected consta... | 10/25/2011 |
| 8015231 | Data processing apparatus and method for performing floating point multiplication A data processing apparatus and method includes multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors. Half adder logic is arranged to produce a plurality of carry and sum bits representing a corresponding ... | 09/06/2011 |
| 7958180 | Multiplier engine A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine h... | 06/07/2011 |
| 7930336 | Large multiplier for programmable logic device A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for... | 04/19/2011 |
| 7844655 | System, method and apparatus for multiplying large numbers in a single iteration using graphs A computer is connected to a memory. The computer to execute an encryption program in the memory. The encryption program including a multiplication portion to perform multiplication of input operands. The multiplication portion includes graph based functions to gene... | 11/30/2010 |
| 7769781 | Method for labeling data stored in sequential data structures with parameters which describe position in a hierarchy A method for calculating numerical values in a manner which can be interpreted as encoding places in a hierarchy, and are in a format convenient for storage and retrieval on computer systems. The numerical values are calculated by associating paths in a hierarchy wi... | 08/03/2010 |
| 7765252 | Five-term karatsuba-variant calculator A technology generally related to large-scale computations employed in the fields of cryptography and data security system employing a new and improved variant of the Karatsuba multiplication approach. The variant of the Karatsuba multiplication approach being utili... | 07/27/2010 |
| 7720901 | Multiplier operable to perform a variety of operations Methods and apparatus are provided for implementing circuitry operable to perform barrel shifting, multiplication, and rotation operations in hard coded logic on a programmable chip. A hard coded multiplier is augmented using multiplexer circuitry, a logical operati... | 05/18/2010 |
| 7689641 | SIMD integer multiply high with round and shift Method, apparatus, and program means for performing a packed multiply high with round and shift operation. The method of one embodiment comprises receiving a first operand having a first set of L data elements. A second operand having a second set of L data elements... | 03/30/2010 |
| 7680872 | Canonical signed digit (CSD) coefficient multiplier with optimization An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in... | 03/16/2010 |
| 7650374 | Hybrid multi-precision multiplication Multiple-precision hybrid multiplication is a technique that takes advantage of row-wise multiplication and column-wise multiplication. To generate a product for multiple-precision operands, partial products of the multiple-precision operands are accumulated in acco... | 01/19/2010 |
| 7640286 | Data processing apparatus and method for performing floating point multiplication A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic for multiplying the first and sec... | 12/29/2009 |
| 7519646 | Reconfigurable SIMD vector processing system A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the... | 04/14/2009 |
| 7506017 | Verifiable multimode multipliers A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same c... | 03/17/2009 |
| 7506016 | Multiplier device Multiplier device comprising first to nth multipliers M1 to Mn for multiplying a carrier modulated information signal with first to nth mutually phase shifted and identical, substantially square wave mixing signals MS... | 03/17/2009 |
| 7418468 | Low-voltage CMOS circuits for analog decoders Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals. Each mu... | 08/26/2008 |
| 7395300 | System, and method for calculating product of constant and mixed number power of two Presented herein are systems and methods for computing the product of a constant and a mixed number power of two. A circuit comprises a first register, a second register, a memory, a third register, and a multiplier circuit. The first register stores the constant. T... | 07/01/2008 |
| 7395299 | System and method for efficient hardware implementation of a perfect precision blending function An apparatus and method for efficiently calculating an intermediate value between a first end value such that the area and time required to implement this operation is minimized is described. The apparatus and method may be used to efficiently multiply a value by a ... | 07/01/2008 |
| 7389317 | Long instruction word controlling plural independent processor operations A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a s... | 06/17/2008 |
| 7364083 | IC card with built-in coprocessor for auxiliary arithmetic, and control method thereof An IC card according to the present invention comprises, a built-in coprocessor for an auxiliary arithmetic in addition to a main arithmetic processing unit, an interval timer for outputting an interrupt request signal upon lapse of a set time shorter than the frame... | 04/29/2008 |
| 7360008 | Enforcing global ordering through a caching bridge in a multicore multiprocessor system The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request compl... | 04/15/2008 |
| 7353244 | Dual-multiply-accumulator operation optimized for even and odd multisample calculations According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed. ... | 04/01/2008 |
| 7349279 | Memory Device Having a Configurable Oscillator for Refresh Operation A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency f... | 03/25/2008 |
| 7334200 | Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. ... | 02/19/2008 |
| 7327198 | Method and system for a polyphase clock for a second intermediate frequency (IF) mixer to improve signal quality Methods and systems for reducing interference in a signal are disclosed herein. Aspects of the method may comprise generating a first local oscillator signal. The generated first local oscillator signal may be phase-shifted to generate a second local oscillator sign... | 02/05/2008 |
| 7319750 | Digital circuit apparatus and method for accelerating preliminary operations for cryptographic processing A digital circuit apparatus and method for cryptographic data processing includes steps and means for determining a first modulus having up to a first number of binary digits. A large integer is received which has up to a second number of binary digits that is great... | 01/15/2008 |
| 7318080 | Split radix multiplication A first number is multiplied by a second number, by representing the first number as a first set of one or more W-bit wide numbers, and representing the second number as a second set of one or more W-bit wide numbers. Each of the W-bit wide numbers from the first se... | 01/08/2008 |
| 7315879 | Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110... | 01/01/2008 |
| 7296049 | Fast multiplication circuits Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier. Generation of a final product is made faster because fewer interstitial pr... | 11/13/2007 |
| 7279936 | Logic basic cell, logic basic cell arrangement and logic device A logic basic cell, a logic basic cell arrangement, and a logic device. A logic basic cell is provided for forming a logic combination of two data signals in accordance with a logic function that can be selected by means of a plurality of logic selection elements, h... | 10/09/2007 |
| 7277540 | Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit... | 10/02/2007 |
| 7271754 | Digital pulse-width modulator A digital pulse-width modulator is provided that receives a digital command input signal and a secondary control input signal and provides a pulse-width-modulated output signal. The pulse-width-modulated output signal comprises a pulse-width that corresponds to an i... | 09/18/2007 |
| 7272624 | Fused booth encoder multiplexer A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results... | 09/18/2007 |
| 7266579 | Combined polynomial and natural multiplier architecture Integrated circuit parallel multiplication circuits, including multipliers that deliver natural multiplication products and multipliers that deliver polynomial products with coefficients over GF(2). A parallel multiplier hardware architecture arranges the addition o... | 09/04/2007 |
| 7266580 | Modular binary multiplier for signed and unsigned operands of variable widths A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-ful... | 09/04/2007 |
| 7257609 | Multiplier and shift device using signed digit representation The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder i... | 08/14/2007 |
| 7242325 | Error correction compensating ones or zeros string suppression An error correction compensating ones or zeros string suppression system and method for use in a digital transmission system is herein disclosed. In digital transmission systems utilizing error control coding (ECC)/forward error correction (FEC) to reduce the number... | 07/10/2007 |
| 7240204 | Scalable and unified multiplication methods and apparatus Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2m)) include processing elements arranged to execute in pipeline stages. The pr... | 07/03/2007 |
| 7236999 | Methods and systems for computing the quotient of floating-point intervals Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and... | 06/26/2007 |
