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| Number | Title | Issue Date |
| 8051124 | High speed and efficient matrix multiplication hardware module A matrix multiplication module and matrix multiplication method are provided that use a variable number of multiplier-accumulator units based on the amount of data elements of the matrices are available or needed for processing at a particular point or stage in the ... | 11/01/2011 |
| 7912889 | Mapping the threads of a CTA to the elements of a tile for efficient matrix multiplication The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs t... | 03/22/2011 |
| 7836118 | Hardware/software-based mapping of CTAs to matrix tiles for efficient matrix multiplication The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs t... | 11/16/2010 |
| 7792894 | Group algebra techniques for operating on matrices A computer system is configured to create a product matrix of data from two matrices of data through the use of a representation in a group algebra. The matrices are represented in a group algebra based on a mathematical group adhering to certain criteria. Then the ... | 09/07/2010 |
| 7792895 | Efficient matrix multiplication on a parallel processing device The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs t... | 09/07/2010 |
| 7774398 | Tonal rotors A set of complex rotations are used to implement a unitary “Q” matrix in which each complex rotation is a set of real rotations, where the minimum number of real rotations to perform the complex rotation is three, and where the minimum number of angles to charac... | 08/10/2010 |
| 7483937 | Parallel processing method for inverse matrix for shared memory type scalar parallel computer A Matrix decomposition (LU decomposition) is carried out on a block E and H. Then, a block B is updated using an upper triangular portion of the block E, and a block D is updated using a lower triangular portion of the block E. At this time, in an LU decomposition, ... | 01/27/2009 |
| 7464130 | Logic circuit and method for performing AES MixColumn transform A logic circuit having structure for performing the AES Rijndael MixColumns transform exploits the relationship between each successive row of the transform matrix and its preceding row. Multiplication of an (m×n) matrix by a (1×n) or by a (m×1) matrix is perform... | 12/09/2008 |
| 7451173 | Fast combinatorial algorithm for the solution of linearly constrained least squares problems A fast combinatorial algorithm can significantly reduce the computational burden when solving general equality and inequality constrained least squares problems with large numbers of observation vectors. The combinatorial algorithm provides a mathematically rigorous... | 11/11/2008 |
| 7363200 | Apparatus and method for isolating noise effects in a signal A matrix includes samples associated with a first signal and samples associated with a second signal. The second signal includes a first portion associated with the first signal and a second portion associated with at least one disturbance, such as white noise or co... | 04/22/2008 |
| 7337205 | Matrix multiplication in a vector processing system To perform multiplication of matrices in a vector processing system, partial products are obtained by dot multiplication of vector registers containing multiple copies of elements of a first matrix and vector registers containing values from rows of a second matrix.... | 02/26/2008 |
| 7321915 | Method and apparatus for efficient matrix multiplication in a direct sequence CDMA system A system and method are disclosed for efficiently performing multiplication of an input vector and an input matrix having a limited number of possible values for any element of the input matrix. Elements of the input matrix are grouped across a second dimension of t... | 01/22/2008 |
| 7318218 | System and method for processor thread for software debugging A system and method for using a processor thread as a debugger is presented. A computer system boots up and initiates a debugger thread. The debugger thread loads a robust, debugger operating system and executes the debugger operating system. Once the debugger threa... | 01/08/2008 |
| 7293248 | System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving paramet... | 11/06/2007 |
| 7293001 | Hybrid neural network and support vector machine method for optimization System and method for optimization of a design associated with a response function, using a hybrid neural net and support vector machine (NN/SVM) analysis to minimize or maximize an objective function, optionally subject to one or more constraints. As a first exampl... | 11/06/2007 |
| 7284027 | Method and apparatus for high speed calculation of non-linear functions and networks using non-linear function calculations for digital signal processing The invention includes apparatus and methods for high-speed calculation of non-linear functions based upon a shifted adder and a offset generator. Various implementations may preferably include a input preprocessor and/or an output post processor. The invention incl... | 10/16/2007 |
| 7236998 | System and method for solving a large system of dense linear equations A method and system for solving a large system of dense linear equations using a system having a processing unit and one or more secondary processing units that can access a common memory for sharing data. A set of coefficients corresponding to a system of linear eq... | 06/26/2007 |
| 7236535 | Reduced complexity channel estimation for wireless communication systems Techniques to derive a channel estimate using substantially fewer number of complex multiplications than with a brute-force method to derive the same channel estimate. In one method, an intermediate vector B is initially derived based on K sub-vectors of a ve... | 06/26/2007 |
| 7216140 | Efficient implementation of n-point DCT, n-point IDCT, SA-DCT and SA-IDCT algorithms An efficient implementation of n-point discrete cosine transform, n-point inverse discrete cosine transform, shape adaptive discrete cosine transform and shape adaptive inverse discrete cosine transform algorithms for multimedia compression and decompression optimiz... | 05/08/2007 |
| 7209939 | Precision improvement method for the Strassen/Winograd matrix multiplication method A computer system for multiplying a first matrix and a second matrix that reduces rounding error, including a processor, a memory, a storage device, and software instructions stored in the memory for enabling the computer system, under the control of the processor, ... | 04/24/2007 |
| 7133040 | System and method for performing an insert-extract instruction An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements... | 11/07/2006 |
| 7126998 | Envelope stabilization method and apparatus A system and method is proposed to significantly reduce the peak to average power ratio (PAPR) for an OFDM system by stabilizing the signal envelope. By using partial response (PR) signaling to spread each sub-symbol over multiple subcarriers, the signal is first co... | 10/24/2006 |
| 7124156 | Apparatus and method for immediate non-sequential state transition in a PN code generator A power of a square matrix is determined in a time approximately proportional to the upper integer of the base-2 logarithm of the order of the matrix. A preferred embodiment uses two types of look-up tables and two multipliers for a matrix of 15×15, and is applied ... | 10/17/2006 |
| 7120658 | Digital systolic array architecture and method for computing the discrete Fourier transform A more computationally efficient and scalable systolic architecture is provided for computing the discrete Fourier transform. The systolic architecture also provides a method for reducing the array area by limiting the number of complex multipliers. In one embodimen... | 10/10/2006 |
| 7107436 | Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 09/12/2006 |
| 7107302 | Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features... | 09/12/2006 |
| 7099812 | Grid that tracks the occurrence of a N-dimensional matrix of combinatorial events in a simulation using a linear index The disclosed invention is a grid that monitors a design simulation to support design verification coverage analysis. The disclosed invention includes n ordered axis declarations 72 that each correspond to a functional attribute and list at least two valid fu... | 08/29/2006 |
| 7093102 | Code sequence for vector gather and scatter Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required complex address calculation hardware and other hardware to perform vector ... | 08/15/2006 |
| 7089275 | Block-partitioned technique for solving a system of linear equations represented by a matrix with static and dynamic entries One embodiment of the present invention provides a system that uses a block-partitioned technique to efficiently solve a system of linear equations. The system first receives a matrix that specifies the system of linear equations to be used in performing a time-base... | 08/08/2006 |
| 7065545 | Computer methods of vector operation for reducing computation time A computer method of vector operations for calculating the inverse of a general square matrix and for solving linear equations systems. The invention comprises a new method of factorization and executing multiply-add operations useful for effecting dot-product opera... | 06/20/2006 |
| 7051059 | Oversampling FIR filter, method for controlling the same, semiconductor integrated circuit having the same, and communication system for transmitting data filtered by the same When changing the number of oversamples is performed, tap factors selected by selectors, which respectively correspond to holding parts in a shift register, are changed back to a predetermined number of tap factors used before the changing of the number of oversampl... | 05/23/2006 |
| 7035332 | DCT/IDCT with minimum multiplication A method, apparatus, computer medium, and other embodiments for discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) of image signals are described. A DCT/IDCT module includes a plurality of different cores. One embodiment of a core includes tw... | 04/25/2006 |
| 7003536 | Reduced complexity fast hadamard transform A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the o... | 02/21/2006 |
| 6996163 | Walsh-Hadamard decoder In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can... | 02/07/2006 |
| 6996702 | Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. T... | 02/07/2006 |
| 6993541 | Fast hadamard peak detector A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the o... | 01/31/2006 |
| 6965909 | Time-division type matrix calculator A matrix calculator calculates multiplication of two matrices. The matrix calculator includes an element selecting portion for selecting elements from elements of the two matrices that would constitute sub-elements of each element of a multiplication result matrix a... | 11/15/2005 |
| 6958718 | Table lookup operation within a data processing system A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result ... | 10/25/2005 |
| 6950844 | Method and apparatus for solving systems of linear inequalities One embodiment of the present invention provides a system that performs a procedure to solve a system of linear inequalities. During operation, the system receives a representation of the system of linear inequalities Ax≦b, wherein Ax≦b can be a linearized form ... | 09/27/2005 |
| 6922717 | Method and apparatus for performing modular multiplication A method and apparatus for performing modular multiplication is disclosed. An apparatus in accordance with one embodiment of the present invention includes a modular multiplier including a plurality of independent computation channels, where the plurality of indepen... | 07/26/2005 |
