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| Number | Title | Issue Date |
| 7565390 | Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (... | 07/21/2009 |
| 7403966 | Hardware for performing an arithmetic function A circuit for performing an arithmetic function on a number performs the function using successive approximation. Each approximation produces an estimate of the result. A determination of the utility of this estimate is made by comparing the inverse function of a gi... | 07/22/2008 |
| 7373370 | Extendable squarer and operation method for processing digital signals An extendable squarer for processing digital signals, suitable for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n−1 bit ex... | 05/13/2008 |
| 7337203 | Exponent calculation apparatus and method, and program An exponent calculation apparatus calculates xe based on input two integers x and e. A pre-calculation module pre-calculates x^{l_i} for each of candidate exponents {l_i} (0≦i≦L−1) stored in a candidate exponents storing unit, the number of the cand... | 02/26/2008 |
| 7320015 | Circuit and method for performing multiple modulo mathematic operations A multi-function modulo processor architecture is capable of performing multiple modulo mathematic operations. The modulo processor includes a pipeline processing portion that iteratively computes a running partial modulo product using the operands of a modulo mathe... | 01/15/2008 |
| 7249154 | Method and apparatus for producing an exponential signal An exponential signal generator having a memory, a scale unit and an adder. A value stored in the memory is scaled and added to itself to produce a new value for storing in the memory. The exponential signal is represented by the exponential value. ... | 07/24/2007 |
| 7188133 | Floating point number storage method and floating point arithmetic device In order to provide a method or the like for storing floating point numbers to make it easier to manage the floating point numbers using a fixed point processor, when a real number x is represented by a*(2^n) where a mantissa is a and an exponent is n, the mantissa ... | 03/06/2007 |
| 7167888 | System and method for accurately calculating a mathematical power function in an electronic device A system and method for accurately calculating a mathematical power function in an electronic device may include an application program that is configured to calculate a direct estimate of power function value for the mathematical power function during a direct line... | 01/23/2007 |
| 7124156 | Apparatus and method for immediate non-sequential state transition in a PN code generator A power of a square matrix is determined in a time approximately proportional to the upper integer of the base-2 logarithm of the order of the matrix. A preferred embodiment uses two types of look-up tables and two multipliers for a matrix of 15×15, and is applied ... | 10/17/2006 |
| 7113593 | Recursive cryptoaccelerator and recursive VHDL design of logic circuits A method and apparatus for performing cryptographic computations employing recursive algorithms to accelerate multiplication and squaring operations. Products and squares of long integer values are recursively reduced to a combination of products and squares reduced... | 09/26/2006 |
| 7111033 | Carry save adders A carry save adder circuit for reducing the number of inputs to a lower number of outputs, the carry save adder circuit including four carry save adders, the four carry save adders being arranged in two layers with the first and second carry save adders being arrang... | 09/19/2006 |
| 7081840 | Decoder for decoding symmetric/asymmetric delay modulation signal and the method thereof The invention relates to a decoder for decoding a received signal to obtain a corresponding decoded bit series. The signal comprises a plurality of pulses. The decoder comprises a memory, a counting module, a transform module, and a logic module. The memory is for s... | 07/25/2006 |
| 7081895 | Systems and methods of multi-pass data processing Method and apparatus for graphics processing is described. More particularly, a graphics processing subsystem capable of multi-pass graphics data processing is described. The graphics processing subsystem includes a geometry processor and a fragment processor, where... | 07/25/2006 |
| 7080114 | High speed scaleable multiplier A high speed scalable multiplier. The high speed scalable multiplier can include a folding multiplier configured to fold multiplicands and multipliers where individual ones of the multiplicands and multipliers exceed a folding threshold. The folding multiplier also ... | 07/18/2006 |
| 7043520 | High-speed/low power finite impulse response filter A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response f... | 05/09/2006 |
| 7016929 | Method and device for calculating a result of an exponentiation For calculating the result of an exponentiation Bd, B being a base and d being an exponent which can be described by a binary number from a plurality of bits, a first auxiliary quantity X is at first initialized to a value of 1. Then a second auxiliary qu... | 03/21/2006 |
| 7007057 | 0.75-power computing apparatus and method and program for use therewith To provide an audio signal quantization device in which an amount of arithmetical operation can be reduced. A 0.75-power computing apparatus includes: an inverse number computing unit; a first −0.5-power computing unit; a multiplication unit; a second −0.5-power... | 02/28/2006 |
| 7003544 | Method and apparatus for generating a squared value for a signed binary number A squaring circuit for signed binary numbers includes a signed binary number modification unit that generates a modified signed binary number. The squaring circuit includes a partial product generation unit that generates partial products that make up a squared valu... | 02/21/2006 |
| 6999981 | Circuit for computing the absolute value of complex numbers An apparatus (100) for computing the absolute value of a complex number includes separate squaring units (110, 115) for the real and imaginary parts. A square root unit (130) extracts the square root of the sum (120) of these squares, whi... | 02/14/2006 |
| 6996179 | Coprocessor circuit architecture, for instance for digital encoding applications A coprocessor circuit for processing image data in digital form, having a motion vector controller block for generating, starting from the image data, motion vector values that include predictor data and macroblock data relating to a current macroblock of the image ... | 02/07/2006 |
| 6993071 | Low-cost high-speed multiplier/accumulator unit for decision feedback equalizers A multiplier device for multiplying one of a discrete set of digital level values with a filter coefficient in a filter device implemented in a decision feedback equalizer including (i) a decoder device for receiving a discrete digital level value to be multiplied a... | 01/31/2006 |
| 6988120 | Arithmetic unit and method thereof A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable... | 01/17/2006 |
| 6963645 | Method for implementing the chinese remainder theorem The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitionin... | 11/08/2005 |
| 6954214 | Efficient perceptual/physical color space conversion An imaging or other sensory reproduction system efficiently converts image or other sensory data between a perceptual color space (e.g., the sRGB color space) and a physical color space (unity gamma) or other perceptual/physical sensory models that are related by an... | 10/11/2005 |
| 6910059 | Apparatus and method for calculating an exponential calculating result of a floating-point number An apparatus for calculating an exponential calculating result for a base 2 floating-point number comprises a transforming device, K exponential tables and a multiplier. The transforming device receives the floating-point number, transforms the floating-point number... | 06/21/2005 |
| 6898615 | Signal processing unit and signal processing method including using an exponent part and a mantissa part for power generation An exponent part extraction section extracts a bit series from the exponent part of an inputted floating point data. A mantissa part extraction section extracts the uppermost K bits from the mantissa part of the floating point data. A first conversion section inputs... | 05/24/2005 |
| 6779015 | Method for implementation of power calculation on a fixed-point processor using table lookup and linear approximation A method for calculating the power of an integer raised to a constant real number. The method may be used to process digital signals, which are encoded in such a fashion as to require such processing. An embodiment of the present invention first receives a segment o... | 08/17/2004 |
| 6775685 | Method and apparatus for calculating energy in a-law or μ-law encoded speech signals An apparatus and method for generating the square of a non-linear encoded signal having a value and a segment number includes an offset generator, a multiplier and a shifter. The offset generator receives the value of the encoded signal and adds an offset value to i... | 08/10/2004 |
| 6766346 | System and method for computing a square of a number A method for computing an intermediate result in squaring a number using a multiplier circuit of predetermined operand size, the method including the steps of representing a number to be squared as a vector of binary digits; grouping the vector into successive segme... | 07/20/2004 |
| 6748412 | Square-and-multiply exponent processor Processing exponents with a square-and-multiply technique that uses a flexible number of bits in the multiply stages. Multiple bits of the exponent can be handled in a single multiply operation, thus reducing the total number of multiply operations required to raise... | 06/08/2004 |
| 6745220 | Efficient exponentiation method and apparatus An encryption/decryption method performs an exponentiation operation on a base number where both the base number and the exponent may be large numbers (i.e., anywhere from 100 to several thousand bits long). The exponent is expressed as a bit string. The bit string ... | 06/01/2004 |
| 6681237 | Exponentiation circuit for graphics adapter A floating point exponentiation circuit suitable for calculating the value BE is disclosed where B and E are floating point values. The floating point exponentiation circuit includes circuitry for producing a value P, where P is approximately e... | 01/20/2004 |
| 6598063 | Fast calculation of (A/B)K by a parallel floating-point processor A method suitable for calculating an expression having the form (A/B)K by a processor that features separate sets of floating point units which can operate in parallel for greater speed of execution. The processor issues instructions to determi... | 07/22/2003 |
| 6578144 | Secure hash-and-sign signatures This invention is a method and apparatus which provide a solution to the problem of constructing efficient and secure digital signature schemes. It presents a signature scheme that can be proven to be existentially unforgeable under a chosen message attac... | 06/10/2003 |
| 6567832 | Device, method, and storage medium for exponentiation and elliptic curve exponentiation An exponent preprocessing unit preprocesses an n-bit exponent k and exponentiates a base A by the preprocessed exponent k. A bit string storing unit stores a bit string including a sign bit and the exponent k. A reading unit reads a bit pattern composed o... | 05/20/2003 |
| 6480873 | Power operation device A power operation device comprises a bit operation unit or performing a bit shift operation on a logarithmic base bit string from a logarithm operation unit according to an input exponent bit string Y, and for furnishing the shifted logarithmic base bit s... | 11/12/2002 |
| 6463452 | Digital value processor The present application relates to a device and method for processing a digital value to thereby determine an estimate of the square of said digital value. This is done by linearly approximating the square function with the help of anchor points that are ... | 10/08/2002 |
| 6460065 | Circuit and method for partial product bit shifting A circuit for shifting the number of partial product bits per column in an adder tree is provided. A partial product bit is generated having a weight 22k that has a 1 value only if one input bit of weight 2.sup.(k-1) has a 0 value while another... | 10/01/2002 |
| 6396926 | Scheme for fast realization of encrytion, decryption and authentication A new scheme for fast realization of encryption, decryption and authentication which can overcome the problems of the RSA cryptosystem is disclosed. The encryption obtains a ciphertext C from a plaintext M according to C.ident.Me (mod n) using ... | 05/28/2002 |
| 6393453 | Circuit and method for fast squaring A circuit for squaring an n-bit value includes a partial product bit generator which logically AND's a bit of the n-bit value having a weight 2k (k is an integer) with the same bit of weight 2k to generate a partial product bit of we... | 05/21/2002 |
