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| Number | Title | Issue Date |
| 7577699 | Apparatus and method for reducing precision of data Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectab... | 08/18/2009 |
| 7340590 | Handling register dependencies between instructions specifying different width registers The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If there is a register dependency between a greater width producer inst... | 03/04/2008 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7230551 | Floating-point type digital signal reversible encoding method, decoding method, apparatuses therefor, and programs therefor Signal samples X in a floating-point format, each of which is composed of 1 bit of sign S, 8 bits of exponent E and 23 bits of mantissa M, are converted through truncation by an integer formatting part 12 into signal samples Y in a 24-bit integer format, the ... | 06/12/2007 |
| 7155472 | Fixed-point quantizer for video coding A quantizer employs a scaled integral inverse ratio division for quantization of an input T by a quantization step Q. The quantizer forms an integral approximation q of 2r/Q by either trunc(2r/Q) or round(2r/Q). A multiplier multipli... | 12/26/2006 |
| 7149766 | Methods for detecting overflow and/or underflow in a fixed length binary field Methods of detecting overflow and/or underflow events are provided. The methods are preferably incorporated into a high-level programming language, but this is not necessary. In one embodiment, an increasing function that may cause overflow for a data element having... | 12/12/2006 |
| 7130876 | Systems and methods for efficient quantization A method in a signal processor for quantizing a digital signal is provided. A fixed-point approximation of a value X÷Q is generated, wherein X is a fixed-point value based on one or more samples in the digital signal, and wherein Q is a fixed-point quantization par... | 10/31/2006 |
| 7085794 | Low power vector summation method and apparatus An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement ... | 08/01/2006 |
| 7080115 | Low-error canonic-signed-digit fixed-width multiplier, and method for designing same An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending u... | 07/18/2006 |
| 7073118 | Apparatus and method for saturating decoder values In one embodiment of the invention, during add-compare-select computations, the output of the adders is guaranteed to be a positive value because the only time normalization logic subtracts a normalization amount is when all accumulators are greater than the normali... | 07/04/2006 |
| 7062526 | Microprocessor with rounding multiply instructions A functional unit in a digital system is provided with a rounding Multiplication instruction, wherein a most significant product of first pair of elements is combined with a least significant product of a second pair of elements, the combined product is rounded, and... | 06/13/2006 |
| 7047396 | Fixed length memory to memory arithmetic and architecture for a communications embedded processor system A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, b... | 05/16/2006 |
| 7035892 | Apparatus and method for reducing precision of data Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectab... | 04/25/2006 |
| 7020788 | Reduced power option A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one... | 03/28/2006 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 02/28/2006 |
| 6996597 | Increasing precision in multi-stage processing of digital signals Precision of multi-stage digital signal processing is increased by preserving least significant bits of one or more output samples of a particular processing stage, having finite word widths, while avoiding the loss of most significant bits. The technique is applica... | 02/07/2006 |
| 6976158 | Repeat instruction with interrupt A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruct... | 12/13/2005 |
| 6970994 | Executing partial-width packed data instructions A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectur... | 11/29/2005 |
| 6957244 | Reduced-width low-error multiplier This invention discloses a reduced-width, low-error multiplier that can be used in Digital Signal Processing (DSP). Specifically, this invention relates to a reduced-width, low-error multiplier capable of processing digital signals of communication systems such as a... | 10/18/2005 |
| 6941329 | Digital method for increasing the calculation accuracy in non-linear functions and hardware architecture for carrying out said method In a digital electronic method for increasing the calculation accuracy in non-linear functions and a system for performing the method, wherein an input format has a strictly defined word but the fixed point may be at different locations, the values are so processed ... | 09/06/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6925553 | Staggering execution of a single packed data instruction using the same circuit A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, ... | 08/02/2005 |
| 6879992 | System and method to efficiently round real numbers The present invention provides a system and method to efficiently round real numbers. The system includes a rounding apparatus to accept an input value that is a real number represented in floating-point format, and to perform a rounding operation on the input value... | 04/12/2005 |
| 6874007 | Apparatus and method for reducing precision of data Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectab... | 03/29/2005 |
| 6801925 | Bit reduction using dither, rounding and error feedback A circuit for reducing the number of bits in a K bit value from K to N bits. The circuit generally comprises a first summing circuit, a control circuit, an error feedback circuit, a second summing circuit, and a processor. The first summing circuit may add an error ... | 10/05/2004 |
| 6792442 | Signal processor and product-sum operating device for use therein with rounding function An object of the present invention is to provide a multiply-accumulate unit with a rounding function which is capable of effecting 16-bit multiply-accumulate operations taking into account the position of an addend in a register. The multiply-accumulate unit with th... | 09/14/2004 |
| 6728739 | Data calculating device and method for processing data in data block form A data calculating device preferably used to improve the calculation precision when fixed-point calculation is performed by block-floating-point system. Each piece of data of a data group is calculated, the minimum scale factor representative of the calculate... | 04/27/2004 |
| 6529929 | Quantization device and method using prime number dividers A quantization circuit includes a set of prime number dividers that can be implemented as look-up tables and a shifter. A shifter implements divisions by prime number (two) and by powers of two. Multiplexing circuitry interconnects the prime number divide... | 03/04/2003 |
| 6401194 | Execution unit for processing a data stream independently and in parallel A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more comp... | 06/04/2002 |
| 6334202 | Fast metric calculation for Viterbi decoder implementation A method and apparatus are used for determining a metric in a decoding algorithm, such as a Viterbi algorithm, using an n-bit processing module, on the basis of plural m-bit soft input words, wherein nࣙ2×m. The technique comprises: receiving plural m-b... | 12/25/2001 |
| 6298368 | Method and apparatus for efficient calculation of an approximate square of a fixed-precision number A bit position, M, that determines the accuracy and efficiency of the approximation is selected from an N bit binary number. The multiplicand is generated by removing the Mth bit from the binary number, shifting the bits of lower order than the Mth bit up... | 10/02/2001 |
| 6148319 | Multiplier There is disclosed a multiplier having a digit rounding function which operates by selecting an added value for rounding a digit in the process of adding partial products, thereby reducing a circuit magnitude and realizing a high-speed operation. A multip... | 11/14/2000 |
| 6115732 | Method and apparatus for compressing intermediate products A processor capable of efficiently performing iterative calculations is disclosed. The processor comprises a multiplier that is configured to perform iterative multiplication operations to evaluate constant powers of an operand such as the reciprocal and ... | 09/05/2000 |
| 6101521 | Data processing method and apparatus operable on an irrational mathematical value A data processing apparatus (200) which improves the accuracy of resultant data. The data processing apparatus includes an input (220, 222) configured to receive input data. The input data includes data corresponding to an input coefficient to be multipli... | 08/08/2000 |
| 6058410 | Method and apparatus for selecting a rounding mode for a numeric operation A processor contains a storage area for a dynamic rounding mode control value, and a circuit coupled to the storage area configured to execute an instruction using a rounding mode. When the instruction is a first predetermined instruction, a first predete... | 05/02/2000 |
| 5930159 | Right-shifting an integer operand and rounding a fractional intermediate result to obtain a rounded integer result A method and apparatus for right-shifting a signed or unsigned integer operand and rounding a fractional intermediate result towards or away from zero to obtain an integer result as prescribed by the MPEG standard in a single instruction cycle is disclose... | 07/27/1999 |
| 5892697 | Method and apparatus for handling overflow and underflow in processing floating-point numbers A method for processing floating-point numbers, each floating-point number having at least sign portion, an exponent portion and a mantissa portion, comprising the steps of converting a floating-point number memory register representation to a floating-po... | 04/06/1999 |
| 5887181 | Method and apparatus for reducing a computational result to the range boundaries of an unsigned 8-bit integer in case of overflow The method and apparatus for checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches, thereby improving instruction processing in a superscalar pipelined processor or an arithmetic... | 03/23/1999 |
| 5835887 | Process for the rapid digital acquisition and processing of analogue measured values in a processor with restricted binary word length In acquisition devices for analog measured values (Ue1 . . . Uen), there is frequently the problem that the digital processor (P) of said devices has a restricted binary word length (WP), as compared with the word length (WP) of the measured values in dig... | 11/10/1998 |
| 5809292 | Floating point for simid array machine A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein floating point operation is based on block shifts of the fr... | 09/15/1998 |
