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| Number | Title | Issue Date |
| 8185572 | Data correction circuit A circuit and method are provided for correcting binary values in a data word having N bit positions where the circuit includes several assemblies, each for a unique data word bit position, where each assembly includes a first logic circuit connected to its unique d... | 05/22/2012 |
| 8140606 | Method and apparatus for a fail safe fourier transform matrix A base station transmitter for maintaining data rate transmission between a set of Fourier Transform matrices, having a digital Fourier Transform Matrix (FTM), and analog FTM, and a plurality of transmit paths therebetween. During the occurrence of a power amplifier... | 03/20/2012 |
| 7941473 | Calculation apparatus and storage medium in which calculation program is stored In a graphing calculator, a decimal calculation unit obtains a calculation result of an arithmetic expression input by an input device to an n-th digit and an (n+m)-th digit. When the values from the most significant digit to an (n+1)-th digit in the (n+m)-digit cal... | 05/10/2011 |
| 7412475 | Error detecting arithmetic circuits using hexadecimal digital roots Embodiments of the invention are directed to circuits and techniques for computer processor register integrity checking employing digital roots, and hexadecimal digital roots (HDRs) in particular, to validate the results of arithmetic operations and register moves. ... | 08/12/2008 |
| 7359429 | Support of the determination of a correlation A method for supporting a determination of the correlation between at least one received code modulated signal and at least one available replica code is shown. In order to reduce the total memory size required for such correlations, the method comprises storing sig... | 04/15/2008 |
| 7340003 | Multi-mode iterative detector A storage system for storing data on a storage medium includes an encoder, a linear block encoder, a write circuit, a read circuit, a channel decoder, and a soft linear block code decoder. In a first iteration, the channel decoder decodes data read by the read circu... | 03/04/2008 |
| 7320037 | Method and apparatus for packet segmentation, enqueuing and queue servicing for multiple network processor architecture A method is described that forms different pieces of a packet and sends each one of the pieces toward a different memory unit amongst a plurality of memory units. Each one of the memory units is managed by a different network processor. The method also receives each... | 01/15/2008 |
| 7315163 | Arithmetic unit In order to correct an overflow of a multiplication result while improving the operation speed, an overflow detection unit detects an overflow based on whether a multiplicand A and a multiplier B are both a negative value with the largest absolute value. A carry-sav... | 01/01/2008 |
| 7278090 | Correction parameter determination system An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop is set to a value equal to the modulus, left shifted one register posi... | 10/02/2007 |
| 7266760 | Method and apparatus for calculating cyclic redundancy checks for variable length packets Cyclic redundancy checking operations may be performed on a message made up of full words and a partial word. An accumulator value for the cyclic redundancy checking operations may be updated as the full words and partial word are processed. The partial word may be ... | 09/04/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7243289 | Method and system for efficiently computing cyclic redundancy checks A method and system is provided for computing a final cyclic redundancy check (CRC) checksum for an entire data block. The method includes segmenting the data block into at least first and second segments and calculating a partial CRC for each segment. A residue tab... | 07/10/2007 |
| 7206800 | Overflow detection and clamping with parallel operand processing for fixed-point multipliers A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixe... | 04/17/2007 |
| 7155471 | Method and system for determining the correct rounding of a function A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and examining the portion of extra precision in the result known as the discrim... | 12/26/2006 |
| 7146396 | Method and apparatus of convolving signals A method of convoluting a first signal (32) and a second signal. The method includes generating a multiplication signal responsive to the second signal, multiplying (34) the first signal by a plurality of time shifted versions of the multiplication sig... | 12/05/2006 |
| 7082451 | Reconfigurable vector-FFT/IFFT, vector-multiplier/divider Systems and methods are described for providing a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes The circuit may be controllably configures to perform a fast Fourier transform function, a multiplier fu... | 07/25/2006 |
| 7035891 | Reduced-hardware soft error detection A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic uni... | 04/25/2006 |
| 7028067 | Generation of mask-constrained floating-point addition and subtraction test cases, and method and system therefor A method and system for generating numerical test cases for testing binary floating-point arithmetic units for addition and subtraction operations, in order to verify the proper operation of the units according to a specified standard. The space for eligible test-ca... | 04/11/2006 |
| 7020550 | Vehicle electronic controller A vehicle electronic controller for checking a control microcomputer with a common monitoring IC, which is used in different vehicles. The vehicle electronic controller includes a control microcomputer, which calculates control data to control an actuator installed ... | 03/28/2006 |
| 7020788 | Reduced power option A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one... | 03/28/2006 |
| 7013321 | Methods and apparatus for performing parallel integer multiply accumulate operations According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. ... | 03/14/2006 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 02/28/2006 |
| 7003041 | Device and method for decoding turbo codes A method and apparatus for decoding turbo codes using a sliding window method is disclosed. In decoding a received sequence using a Maximum A Posteriori (MAP) algorithm, a learning by a backward processing is performed for a predetermined length and first resultant ... | 02/21/2006 |
| 7003543 | Sticky z bit The indication of a status affected by the performance of an ALU mathematical operation is provided. The indication includes the setting and clearing of a status bit in a status register based on the production of an arithmetic result of zero by an ALU performing th... | 02/21/2006 |
| 6978443 | Method and apparatus for organizing warning messages The present invention is a method and apparatus for organizing warning messages generated by a computer program analyzer. A computer program analyzer generates a set of warning messages based upon potentially erroneous portions of a computer program, where each warn... | 12/20/2005 |
| 6975679 | Configuration fuses for setting PWM options Configuration bits are provided that configure PWM outputs of a processor incorporating a PWM module. The configuration bits cause the PWM module to put the PWM outputs into tri-state, active high or active low modes when the PWM module is inactive or when individua... | 12/13/2005 |
| 6958718 | Table lookup operation within a data processing system A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result ... | 10/25/2005 |
| 6952711 | Maximally negative signed fractional number multiplication A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative re... | 10/04/2005 |
| 6941329 | Digital method for increasing the calculation accuracy in non-linear functions and hardware architecture for carrying out said method In a digital electronic method for increasing the calculation accuracy in non-linear functions and a system for performing the method, wherein an input format has a strictly defined word but the fixed point may be at different locations, the values are so processed ... | 09/06/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6922159 | Apparatus and method for decoding Coding section 205 recodes decoded data stored in decoded data storage section 204, data conversion section 206 converts data “0” and “1” output from coding section 205 to “1” and “−1” respectively, sum-of-product calcul... | 07/26/2005 |
| 6914983 | Method for checking modular multiplication The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitionin... | 07/05/2005 |
| 6829308 | Satellite communication system utilizing low density parity check codes An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) cod... | 12/07/2004 |
| 6779014 | Cyclic step by step decoding method used in discrete fourier transform cyclic code of a communication system Discrete Fourier transformation is applied to an analog system so that a signal be transfering, the analog data can be corrected before being quantized and after being transferred and received. In the DFT cyclic decoder and the method of the same, a cyclic property ... | 08/17/2004 |
| 6772185 | Time-series predicting method using wavelet number series and device thereof An object is to provide a time-series prediction method and apparatus utilizing wavelet coefficient series which can accurately predict a prediction value of an original time series. When a time-series prediction utilizing wavelet coefficient series is perfor... | 08/03/2004 |
| 6754542 | Control arithmetic apparatus and method A control arithmetic device includes a subtracting section, disturbance application detecting section, error correction amount calculating section, error correction amount convergence calculating section, and control arithmetic section. The subtracting section calcu... | 06/22/2004 |
| 6718276 | Method and apparatus for characterizing frequency response on an error performance analyzer A method and apparatus for characterizing frequency response of a device under test (DUT) is disclosed. A repeated base bit pattern is received, the base bit pattern including a first transition from a 0-bit to a 1-bit. Then, using bit error rate distribution, multi... | 04/06/2004 |
| 6643678 | Correction of code drift in a non-coherent memory An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver can include a Doppler correction circuit, which permits correlation data with frequency shift in the code to be non-coherently integrated among relatively f... | 11/04/2003 |
| 6629125 | Storing a frame header A method and apparatus for use with a computer system are disclosed. A packet is received that includes a header. The header indicates at least one characteristic that is associated with a layer of a protocol stack. The packet is parsed in hardware to ext... | 09/30/2003 |
| 6519620 | Saturation select apparatus and method therefor A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigne... | 02/11/2003 |
