Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8015230 | Fast modular zero sum and ones sum determination In one embodiment, a state determiner comprises a plurality of logic circuits and a second logic circuit. Each logic circuit corresponds to a respective bit position of a result of an adder. A first logic circuit corresponds to a least significant bit of the result ... | 09/06/2011 |
| 7444367 | Floating point status information accumulation circuit A floating point flag combining or accumulating circuit includes an analysis circuit that receives a plurality of floating point operands, each having encoded status flag information, and a result assembler. The analysis circuit analyzes the plurality of floating po... | 10/28/2008 |
| 7430576 | Floating point square root provider with embedded status information A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit co... | 09/30/2008 |
| 7395297 | Floating point system that represents status flag information within a floating point operand A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one embodiment, a floating point ope... | 07/01/2008 |
| 7363337 | Floating point divider with embedded status information A system for providing floating point division includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and da... | 04/22/2008 |
| 7333965 | Classifying text in a code editor using multiple classifiers Multiple independent classifiers of a code editor are used to classify a range of text. Each classifier is an independent classifier and can independently classify any given range of text. Classifiers can be added and merged during run time of the code editor. Addin... | 02/19/2008 |
| 7293020 | String search scheme in a distributed architecture Methods and apparatuses for searching network data for one or more predetermined strings are disclosed. A multi-stage search may be performed by different hardware components. In a first search stage, a first processor may perform a comparison of blocks of incoming ... | 11/06/2007 |
| 7290027 | Circuit suitable for use in a carry lookahead adder An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the fir... | 10/30/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7242414 | Processor having a compare extension of an instruction set architecture A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision ... | 07/10/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7216140 | Efficient implementation of n-point DCT, n-point IDCT, SA-DCT and SA-IDCT algorithms An efficient implementation of n-point discrete cosine transform, n-point inverse discrete cosine transform, shape adaptive discrete cosine transform and shape adaptive inverse discrete cosine transform algorithms for multimedia compression and decompression optimiz... | 05/08/2007 |
| 7211035 | Method for manufacturing reclosable packaging bag A reclosable packaging bag comprises a main bag body having an opening portion and at least one heat-sealed portion; and a linear fastener provided on the opening portion of the main bag body. The linear fastener is provided along the opening portion of the main bag... | 05/01/2007 |
| 7188168 | Method and apparatus for grammatical packet classifier A packet classification language (GPCL) is provided to specify protocol hierarchies among data packets in a routing device. The GPCL uses regular expressions to match incoming data packets and a syntax to describe the protocol hierarchy. A GPCL compiler produces an ... | 03/06/2007 |
| 7185081 | Method and apparatus for programmable lexical packet classifier A packet classification language (PCL) is provided to specify data packets in a routing device. The PCL uses regular expressions to match incoming data packets. Class identifiers associated with each regular expression identifies the class to which each recognized p... | 02/27/2007 |
| 7155440 | Hierarchical data processing Some embodiments of the invention provide a method for processing a hierarchical data structure that includes a parent data set and first and second child data sets of the parent data set. The parent and first and second child data sets includes several data tuples.... | 12/26/2006 |
| 7085940 | Floating point unit power reduction via inhibiting register file write during tight loop execution A system and method for reducing the power consumption in a floating point unit of a processor executing an iterative loop of a program by inhibiting floating point register file writes of interim values of the loop from the floating point multiply adder (FPMADD) un... | 08/01/2006 |
| 7071935 | Graphics system with just-in-time decompression of compressed graphics data A graphics system and method for increasing efficiency of decompressing blocks of compressed geometry data and reducing redundant transformation and lighting calculations is disclosed. Multiple decompression pipelines are used to increases the decompression speed. A... | 07/04/2006 |
| 7069289 | Floating point unit for detecting and representing inexact computations without flags or traps A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a sep... | 06/27/2006 |
| 7062633 | Conditional vector arithmetic method and conditional vector arithmetic unit It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150, the result of the decision is retained as a state flag, and it is decided by a condition decision... | 06/13/2006 |
| 7058678 | Fast forwarding ALU An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second binary number comprise: a first arithmetic logic unit (ALU) operating... | 06/06/2006 |
| 7047272 | Rounding mechanisms in processors An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate carry results and provides a final output to a final adder ... | 05/16/2006 |
| 7042885 | System and method for implementing a distributed service platform using a system-wide switchtag definition A system and method for configuring components of a distributed routing platform using switchtags. The distributed routing platform includes transport service modules that are configured to perform a service on packets. Each of the transport service modules is furth... | 05/09/2006 |
| 7031297 | Policy enforcement switching A method of performing policy enforcement by a switch, including receiving a plurality of frames, examining at least some of the received frames to determine whether they require non-default policy enforcement according to pre-programmed policy rules which pertain t... | 04/18/2006 |
| 7028069 | Dynamic circuit using exclusive states The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of ... | 04/11/2006 |
| 7020788 | Reduced power option A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one... | 03/28/2006 |
| 7016928 | Floating point status information testing circuit A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may sup... | 03/21/2006 |
| 7010562 | Arithmetic circuit An arithmetic circuit includes an arithmetic circuit performing an arithmetic operation of a predetermined bit width in accordance with an arithmetic instruction, a holding circuit storing status information about the arithmetic operation by the arithmetic circuit a... | 03/07/2006 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 02/28/2006 |
| 7003543 | Sticky z bit The indication of a status affected by the performance of an ALU mathematical operation is provided. The indication includes the setting and clearing of a status bit in a status register based on the production of an arithmetic result of zero by an ALU performing th... | 02/21/2006 |
| 7003650 | Method for prioritizing operations within a pipelined microprocessor based upon required results A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the e... | 02/21/2006 |
| 6996596 | Floating-point processor with operating mode having improved accuracy and high performance Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes an operand processing section and an operand flush section. For each... | 02/07/2006 |
| 6986023 | Conditional execution of coprocessor instruction based on main processor arithmetic flags A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a targ... | 01/10/2006 |
| 6975679 | Configuration fuses for setting PWM options Configuration bits are provided that configure PWM outputs of a processor incorporating a PWM module. The configuration bits cause the PWM module to put the PWM outputs into tri-state, active high or active low modes when the PWM module is inactive or when individua... | 12/13/2005 |
| 6976158 | Repeat instruction with interrupt A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruct... | 12/13/2005 |
| 6970898 | System and method for forcing floating point status information to selected values A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined for... | 11/29/2005 |
| 6965985 | Sign generation bypass path to aligner for reducing signed data load latency A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part of the data. The sign bit is transferred to the aligner along the by... | 11/15/2005 |
| 6954842 | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex... | 10/11/2005 |
| 6952711 | Maximally negative signed fractional number multiplication A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative re... | 10/04/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
