Class 708/522 - Systolic

Subclass of Class 708 - Electrical computers: arithmetic processing and calculating
Definition: Subject matter wherein the operation is effected by a specific
No. of patents: 20
Last issue date: 10/23/2007

Number	Title	Issue Date
7287113	Method of and apparatus for controlling bidirectional streams of isochronous data flowing between an application and a bus structure An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any number of ...	10/23/2007
7103700	Method of and apparatus for controlling bidirectional streams of isochronous data flowing between an application and a bus structure An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any number of ...	09/05/2006
7016815	Performance assessment of data classifiers A method for operating a data classifier operable to generate an element of output data in response to an element of input data, such as a neural network, is disclosed. The method includes using the data classifier to generate elements of result output data in respo...	03/21/2006
6950150	Method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween A method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween. Standard definition and progressive scan digital video signals which are clocked at first and s...	09/27/2005
6904475	Programmable first-in first-out (FIFO) memory buffer for concurrent data stream handling A programmable FIFO receives a stream of data to be buffered within the FIFO and then output from the FIFO. The programmable FIFO includes the ability to receive program instructions from an application or control circuit to perform specific operations on the stream...	06/07/2005
5948053	Digital signal processor architecture using signal paths to carry out arithmetic operations A digital signal processor has an arithmetic operation device that carries out arithmetic operations. The arithmetic operation device has a plurality of elementary arithmetic operation units. A signal path-forming device forms signal paths for inputting a...	09/07/1999
5864693	Movement control method and chaotic information processing unit using chaotic neural network, and group movement control method This invention discloses a method of realizing a variety of movements which are controlled while maintaining their complexity by generating complex movements, which appear irregular at a glance, by the deterministic method. A neural network which connects...	01/26/1999
5740092	Signal processor In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arit...	04/14/1998
5530953	Apparatus for relocating spatial information for use in data exchange in a parallel processing environment The apparatus includes a plurality of groups of plural data paths which are connected in such a manner that each data path of one group intersects with one or more data paths of another or more data path groups. Each data path of each group is composed of...	06/25/1996
5422836	Circuit arrangement for calculating matrix operations in signal processing Circuit arrangement for calculating matrix operations, such as those which recur frequently in signal processing, specifically in conjunction with neural networks, having a systolic array of multipliers and adders, downstream from which a recursive accumu...	06/06/1995
5319587	Computing element for neural networks A computing element for use in an array in a neural network. Each computing element has K (K>1) input signal terminals, K input backpropagated signal terminals, K output backpropagated signal terminals and at least one output terminal. The input terminals...	06/07/1994
5148385	Serial systolic processor A serial systolic processor for performing neural network functions. A serial processor (90) provides the digital processing circuits for processing an input serial data stream applied to a serial input (20). A memory (29) stores digital signals represent...	09/15/1992
5058001	Two-dimensional array of processing elements for emulating a multi-dimensional network Two-dimensional mesh architecture in an array processor of myriad processing elements allows relative ease in manufacturing, using planar integrated circuits and predominant X, Y connections. There is a need, in any array processor, to connect a selected ...	10/15/1991
4972361	Folded linear systolic array Circuit for computing values of the elements of a triangular matrix, where ##EQU1## similar subcircuits provide CORDIC processing and memory, the subcircuits connected in a folded systolic array, the first subcircuit providing input capability to the...	11/20/1990
4922418	Method for controlling propogation of data and transform through memory-linked wavefront array processor A method for performing computations with an asynchronous linear array of multiple processing stages is disclsoed. The linear array comprises multiple processing stages interspersed with flow control flag mechanisms and with dual port linking memories. Th...	05/01/1990
4817028	Device for summing of squares This device for summing squares is designed to calculate the sum of the squares of "n" numbers with "m" binary elements, where n and m are whole numbers equal to or greater than "2"; it is made up from a systolic network 14 formed of identical cells arran...	03/28/1989
4807183	Programmable interconnection chip for computer system functional modules The interconnection chip of the present invention is a custom chip which is designed to serve as an efficient link between system functional modules, such as arithmetic units, register files and input/output ports. The chip includes a crossbar interconnec...	02/21/1989
4745546	Column shorted and full array shorted functional plane for use in a modular array processor and method for using same A column shorted and full array shorted functional plane for simultaneously transferring, or shorting, data to and from the data exchange subsystems of the array processor. This functional plane nominally includes an array of pseudo-modules that architect...	05/17/1988
4727503	Systolic array A systolic array of cells for processing a data stream includes an arrangement of nearest-neighbor connected boundary cells, internal cells and a multiplier, arranged as a triangular array and a column. The boundary cells are diagonally interconnected. Ea...	02/23/1988
4720780	Memory-linked wavefront array processor A Memory-Linked Wavefront Array Processor (MWAP) is disclosed which computes a broad range of signal processing, scientific and engineering problems at ultra-high speed. The memory-linked wavefront array processor is an array of identical programmable pro...	01/19/1988

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Class 708/522 - Systolic