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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 7844654 | Arithmetic unit of arbitrary precision, operation method for processing data of arbitrary precision and electronic equipment An arithmetic unit of arbitrary-precision, including: a main processing unit, which splits up the first and the second arbitrary-precision values into N-bit (where N is a natural number) operands respectively in the-least-significant-bit-first order for computing wi... | 11/30/2010 |
| 7428567 | Arithmetic unit for addition or subtraction with preliminary saturation detection An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithm... | 09/23/2008 |
| 7366305 | Platform and method for establishing trust without revealing identity One aspect of an embodiment of the invention provides a method and platform to prove to a challenger that a responder device possesses cryptographic information from a certifying manufacturer. This is accomplished by performing a direct proof by the responder device... | 04/29/2008 |
| 7219118 | SIMD addition circuit A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a sum of each set of binary numbers. Each set of numbers defines a disti... | 05/15/2007 |
| 7171496 | Data bus width conversion apparatus and data processing apparatus A data bus width conversion apparatus is provided for receiving N-bit data from a first device having a first bus width and outputting the N-bit data to a second device having a second bus width. The first device divides the N-bit data into a plurality of bit data g... | 01/30/2007 |
| 7157934 | Programmable asynchronous pipeline arrays High-performance, highly pipelined asynchronous FPGAs employ a very fine-grain pipelined logic block and routing interconnect architecture. These FPGAs, which do not use a clock to sequence computations, automatically “self-pipeline” their logic without the desi... | 01/02/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7149768 | 3-input arithmetic logic unit A 3-input adder/subtractor unit, having a first input for receiving a first operand A, a second input for receiving a second operand B, and a third input for receiving a third operand C. An add/subtract unit includes a control input for receiving a user-specified op... | 12/12/2006 |
| 7062637 | DSP operations with permutation of vector complex data type operands Executing digital signal processing (DSP) instructions in a digital signal processor integrated circuit comprising receiving a DSP instruction in digital signal processor integrated circuit to process one or more complex number operands; fetching a first operand wit... | 06/13/2006 |
| 7058678 | Fast forwarding ALU An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second binary number comprise: a first arithmetic logic unit (ALU) operating... | 06/06/2006 |
| 7051062 | Apparatus and method for adding multiple-bit binary-strings Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second... | 05/23/2006 |
| 7027514 | Distributed video stream decoding system on computer and decoding method of the same A distributed video stream decoding system on computer and decoding method of the system is proposed to increase the decoding efficiency. The decoding method reads pictures of video stream and divides each picture into a plurality of slice packages through software ... | 04/11/2006 |
| 7020726 | Methods and apparatus for signaling to switch between different bus bandwidths The present invention provides an apparatus and method for selecting bus-width formats. In an exemplary preferred embodiment of the invention, the circuit includes a bus controller configured to provide a first bus-width control signal to select a first bus-width. T... | 03/28/2006 |
| 7017033 | Arithmetic apparatus and arithmetic method An arithmetic apparatus and an arithmetic method capable of executing arithmetic by reconfigurable hardware, shortening the processing time of arithmetic including conditional branches causing a heavy processing load and improving the processing speed even when cond... | 03/21/2006 |
| 7003543 | Sticky z bit The indication of a status affected by the performance of an ALU mathematical operation is provided. The indication includes the setting and clearing of a status bit in a status register based on the production of an arithmetic result of zero by an ALU performing th... | 02/21/2006 |
| 6970994 | Executing partial-width packed data instructions A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectur... | 11/29/2005 |
| 6959316 | Dynamically configurable processor A data processor, such as a DSP, includes a multiplier block having a multiplier front end for generating partial products from input operands, and further includes a plurality of ALUs having inputs that are switchably or programmably coupled, in a first mode of ope... | 10/25/2005 |
| 6925553 | Staggering execution of a single packed data instruction using the same circuit A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, ... | 08/02/2005 |
| 6883012 | Linear-to-log converter for power estimation in a wireless data network receiver A converter to convert an N-bit input in a linear scale to an M-bit output in a logarithmic scale. The converter includes a set of K subrange converters each coupled to a respective number of bits of the N-bit input that represents a subrange of the N-bit input, eac... | 04/19/2005 |
| 6813627 | Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operands Integer multiply operations using data stored in an integer register file are performed using multi-media primitive instructions that operate on smaller operands. The present invention performs a multiply operation on a 32-bit or 64-bit value by performing multiply ... | 11/02/2004 |
| 6795841 | Parallel processing of multiple data values within a data word When performing data processing operations upon data words 2, 4 including a plurality of abutting data values a0, a1, a2, a3, b0, b1, b2 and b3 the results of the operation upon one data value may influe... | 09/21/2004 |
| 6748411 | Hierarchical carry-select multiple-input split adder An adder or an integrated circuit including an adder, includes a hierarchical carry-select split adder capable of operating in a split mode of operation when a mode select input takes on a first state. It is also capable of operating in a hierarchical carry-select m... | 06/08/2004 |
| 6732126 | High performance datapath unit for behavioral data transmission and reception A programmable and configurable datapath unit (DPU) includes a configuration of single-bit multi-function processing units (PUs). The DPU can perform any of a variety of functions depending on the control applied to each PU. Functionality can be increased by utilizi... | 05/04/2004 |
| 6725360 | Selectively processing different size data in multiplier and ALU paths in parallel An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with the first path, and includes smaller units which process data up to n 2... | 04/20/2004 |
| 6557020 | Information processing system, enciphering/deciphering system, system LSI, and electronic apparatus An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units (7-1 to 7-x), each comp... | 04/29/2003 |
| 6557096 | Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types A signal processor with an instruction set architecture (ISA) for flexible data typing, permutation, and type matching of operands. The signal processor includes a data typer and aligner to support flexible data typing, permutation and type matching of op... | 04/29/2003 |
| 6502119 | High speed microprocessor zero detection circuit with 32-bit and 64-bit modes A zero-detection circuit is provided. The zero-detection circuit includes a plurality of transistor stacks. Each transistor stack includes an input transistor and a clocked transistor. Each of the plurality of input transistors receives a data input. An i... | 12/31/2002 |
| 6460064 | Multiplier for operating n bits and n/2 bits and method therefor A multiplier for multiplying n bits and n/2 bits is disclosed, wherein a word multiplication is implemented by input of two words. The apparatus includes an encoder receiving the two words and pretreating one of the two words, a partial product generating... | 10/01/2002 |
| 6449629 | Three input split-adder An integrated circuit includes an adder having a first adder circuit for receiving a portion of the operands to be summed, along with corresponding carry-in inputs. The first adder circuit provides a sum output and carry-out outputs. A second adder circui... | 09/10/2002 |
| 6408320 | Instruction set architecture with versatile adder carry control A data processing circuit has an adder unit divided into plural sections. Each section receives a subset of the bits of the operands and generates a subset of the bits of the resultant. A carry multiplexer is disposed between the sections. This carry mult... | 06/18/2002 |
| 6301600 | Method and apparatus for dynamic partitionable saturating adder/subtractor An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-... | 10/09/2001 |
| 6260055 | Data split parallel shifter and parallel adder/subtractor Shift of input data without split by a shifter, generation of code extension data by a code extension data generator, and generation of a mask signal by a mask signal generator are carried out in parallel. The mask signal generator generates the mask sign... | 07/10/2001 |
| 6253299 | Virtual cache registers with selectable width for accommodating different precision data formats A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in ... | 06/26/2001 |
| 6202077 | SIMD data processing extended precision arithmetic operand format Two related extended precision operand formats provide for efficient multiply/accumulate operations in a SIMD data processing system. Each format utilizes a group of "b" bit elements in a vector register. Each of the elements provides "m" bits of precisio... | 03/13/2001 |
| 6188240 | Programmable function block A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first ... | 02/13/2001 |
| 6041341 | Method and circuit for adding operands of multiple size A circuiting method is disclosed for adding operands of multiple size. This circuit and method employ an n bit adder having n first and second inputs. A first m bit operand is inputted into the m least significant first inputs of the adder, where n is gre... | 03/21/2000 |
| 6035318 | Booth multiplier for handling variable width operands A circuit for generating partial products for variable width multiplication operations is provided. According to an embodiment of the present invention, the circuit includes a plurality of partial product selector groups, each partial product selector gro... | 03/07/2000 |
| 6032170 | Long instruction word controlling plural independent processor operations A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of prod... | 02/29/2000 |
| 6003125 | High performance adder for multiple parallel add operations An adder unit for a microprocessor, being capable, in response to a first control signal, of adding two full word data values, stored in a first storage location and in a second storage location, respectively, and being capable, in response to a second co... | 12/14/1999 |
| 5991868 | Apparatus and method for processing data with a plurality of flag groups In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups which are changed in correspondence to data having differe... | 11/23/1999 |
