Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 8024394 | Dual mode floating point multiply accumulate unit Included are embodiments of a Multiply-Accumulate Unit to process multiple format floating point operands. For short format operands, embodiments of the Multiply Accumulate Unit are configured to process data with twice the throughput as long and mixed format data. ... | 09/20/2011 |
| 7716267 | Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium Decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in calculation instruction, comprises multidigit memory section capable of storing values with greater numbers of digits than the number of digits ... | 05/11/2010 |
| 7668897 | Result partitioning within SIMD data processing systems Within a processor 2 providing single instruction multiple data (SIMD) type operation, single data processing instructions can serve to control processing logic 4, 6, 8, 10 to perform SIMD-type processing operations upon multiple independent input valu... | 02/23/2010 |
| 7483936 | Calculating unit A calculating unit including a number of bit slices which is less than the number of positions of the operand to be processed. Each bit slice has a logic element and a communication bus between the logic element and the plurality of register cells. The register cell... | 01/27/2009 |
| 7397399 | Method and device for transcoding N-bit words into M-bit words with M smaller N The present invention concerns a method for transcoding a N bits word into a M bits word with M | 07/08/2008 |
| 7340590 | Handling register dependencies between instructions specifying different width registers The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If there is a register dependency between a greater width producer inst... | 03/04/2008 |
| 7330964 | Microprocessor with independent SIMD loop buffer An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of instruction and a second type of instruction and a co-processor configured to execute the loop detected b... | 02/12/2008 |
| 7320013 | Method and apparatus for aligning operands for a processor A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second opera... | 01/15/2008 |
| 7284117 | Processor that predicts floating point instruction latency based on predicted precision A processor includes a prediction circuit and a floating point unit. The prediction circuit is configured to predict an execution latency of a floating point operation. The floating point unit is coupled to receive the floating point operation for execution, and is ... | 10/16/2007 |
| 7272622 | Method and apparatus for parallel shift right merge of data A method for a parallel shift right merge of data. The method of one embodiment comprises receiving a shift count of M. A first operand having a first set of L data elements is shifted left by ‘L−M’ data elements. A second operand having a second set of L data... | 09/18/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7107435 | System and method for using hardware assist functions to process multiple arbitrary sized data elements in a register A system and method for processing multiple arbitrary sized data elements in a register. A method of the invention comprises the steps of: creating a mask register that defines a set of arbitrary sized segments for a register; storing a plurality of arbitrary sized ... | 09/12/2006 |
| 7062637 | DSP operations with permutation of vector complex data type operands Executing digital signal processing (DSP) instructions in a digital signal processor integrated circuit comprising receiving a DSP instruction in digital signal processor integrated circuit to process one or more complex number operands; fetching a first operand wit... | 06/13/2006 |
| 7047271 | DSP execution unit for efficient alternate modes for processing multiple data sizes In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second processing path is processes (n/2)-bit data. The multiple processing ... | 05/16/2006 |
| 7043518 | Method and system for performing parallel integer multiply accumulate operations on packed data A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one ... | 05/09/2006 |
| 7039906 | Compiler for enabling multiple signed independent data elements per register A compiler for data processing outputs lower-level code for packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and when executed, the code simultaneously operates on the elements in a register in a singl... | 05/02/2006 |
| 7020788 | Reduced power option A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one... | 03/28/2006 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 02/28/2006 |
| 7003543 | Sticky z bit The indication of a status affected by the performance of an ALU mathematical operation is provided. The indication includes the setting and clearing of a status bit in a status register based on the production of an arithmetic result of zero by an ALU performing th... | 02/21/2006 |
| 6975679 | Configuration fuses for setting PWM options Configuration bits are provided that configure PWM outputs of a processor incorporating a PWM module. The configuration bits cause the PWM module to put the PWM outputs into tri-state, active high or active low modes when the PWM module is inactive or when individua... | 12/13/2005 |
| 6976158 | Repeat instruction with interrupt A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruct... | 12/13/2005 |
| 6959317 | Method and apparatus for increasing processing performance of pipelined averaging filters A pipelined processor such as an averaging filter including at least one subtractor section and at least one adder section. Both of the subtractor section and the adder section have a plurality of adder logic units. In comparison to the conventional processor, the p... | 10/25/2005 |
| 6952711 | Maximally negative signed fractional number multiplication A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative re... | 10/04/2005 |
| 6937757 | Implementation and uses of XsRGB An extended colorspace which has a higher accuracy and a wider gamut than sRGB color space is disclosed. The extended color space includes an alpha channel which defines the translucency of the color image. The alpha channel is different from known alpha channels in... | 08/30/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6854001 | Apparatus and method for simultaneously displaying a number along with its number of significant figures A computing device (40) comprises an electrical circuit and a software application. A display screen (138) and an input device (140) are electrically coupled to the electrical circuit. The software application provides instructions to determine ... | 02/08/2005 |
| 6681236 | Method of performing operations with a variable arithmetic The process for performing operations with a variable arithmetic does not call for any shifting of the data in the different registers that come into play in the operation. The input registers can have empty parts which are completed by appropriate bit se... | 01/20/2004 |
| 6629231 | System and method for efficient register file conversion of denormal numbers between scalar and SIMD formats There is disclosed a pipelined floating point unit comprising: a) a first plurality of pipelined functional units for processing operands conforming to a single instruction-multiple data stream (SIMD) instruction set architecture (ISA); b) a second plural... | 09/30/2003 |
| 6564238 | Data processing apparatus and method for performing different word-length arithmetic operations A digital signal processing system performs different word-length arithmetic operations (e.g., 24-bit arithmetic and 16-bit arithmetic) using the same hardware. The digital signal processing system includes internal buses, a host processor coupled to the ... | 05/13/2003 |
| 6557096 | Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types A signal processor with an instruction set architecture (ISA) for flexible data typing, permutation, and type matching of operands. The signal processor includes a data typer and aligner to support flexible data typing, permutation and type matching of op... | 04/29/2003 |
| 6523057 | High-speed digital accumulator with wide dynamic range A high-speed, wide dynamic range, digital accumulator includes a first adder stage in which an input addend is added to a value of a least significant part of an output of an accumulator from a preceding clock period. The accumulator also includes at leas... | 02/18/2003 |
| 6463525 | Merging single precision floating point operands Where it is desired to perform a double precision operation using single precision operands, first and second single precision operands are loaded into first and second respective rows of a re-order buffer, and third and fourth single precision operands a... | 10/08/2002 |
| 6460135 | Data type conversion based on comparison of type information of registers and execution result In a microprocessor, a type information comparator compares type information of an execution result of an instruction with type information of the type information register corresponding to the data register which is requested by said instruction, and gen... | 10/01/2002 |
| 6311199 | Sign extension unit A sign extension unit has first and second sign extenders to extend a sign bit, i.e., the most significant bit of input data to the higher side of the input data. The input data is divided into n-bit blocks. The first sign extender carries out sign extens... | 10/30/2001 |
| 6253299 | Virtual cache registers with selectable width for accommodating different precision data formats A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in ... | 06/26/2001 |
| 6163764 | Emulation of an instruction set on an instruction set architecture transition A method and apparatus for emulating an instruction on a processor. The instruction operates on an operand in a first data format and the processor operates in a second data format. The operand is converted from the first data format to the second data fo... | 12/19/2000 |
| 6138135 | Propagating NaNs during high precision calculations using lesser precision hardware A floating point arithmetic unit provides consistent propagation of NaNs le performing high precision calculations on hardware designed to perform lower precision calculations. In one embodiment, the floating point arithmetic unit is provided with a micr... | 10/24/2000 |
| 6094719 | Reducing data dependent conflicts by converting single precision instructions into microinstructions using renamed phantom registers in a processor having double precision registers In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision floating-point arithmetic operation having four possible register dependencies is converted into two m... | 07/25/2000 |
| 6049865 | Method and apparatus for implementing floating point projection instructions A floating point unit (60) capable of executing projection instructions provides performance improvement in multiple precision floating point arithmetic. The projection instructions provide for obtaining partial sequences of numbers, products, and sums wh... | 04/11/2000 |
