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Safety System For Remove a Rider From a Vehicle by Deploying a Parachute
Methods and apparatus for reducing the velocity of a rider in or on an open cockpit vehicle when the rider is thrown from the vehicle.
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| Number | Title | Issue Date |
| 7805481 | Exploitation of topological categorization of chaotic and fractal functions, including field line calculations A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions, including the calculation of both potential for complex and hypercomplex and f... | 09/28/2010 |
| 7801939 | Complex and hypercomplex inclusive interval expression evaluations with stable numeric evaluations and precision efficacy testing Improvements to optimal interval operators are developed for interval expression evaluation using arithmetic and real power operators applied to complex and hypercomplex number systems. A method for determining efficacy of numeric precision, incorporating minor chan... | 09/21/2010 |
| 7051061 | Dual use dual complex multiplier and complex divider A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth c... | 05/23/2006 |
| 5473557 | Complex arithmetic processor and method A complex arithmetic processor and method includes a host interface for distributing data, a left memory and a right memory each coupled to the host interface, and a Z memory coupled to the host interface. The left memory and the right memory store the da... | 12/05/1995 |
| 5459681 | Special functions arithmetic logic unit method and apparatus A special functions arithmetic logic unit (ALU) method and apparatus includes an ALU register, an ALU register value processor coupled to the ALU register for receiving and processing ALU register values to produce output data, and a normalizer. The norma... | 10/17/1995 |
| 5053987 | Arithmetic unit in a vector signal processor using pipelined computational blocks An arithmetic unit for a vector signal processor implements IEEE Standard 754 for Floating-Point Arithmetic. The arithmetic unit includes three pipelined floating-point computational blocks: a multiplier, an adder-subtracter, and an adder to provide for h... | 10/01/1991 |
| 5010509 | Accumulator for complex numbers An intermediate storage register is added to the combinational logic of an accumulator and is located so that a second term may be stored in the first half of an adder array, while a first term continues the accumulation process in the second half of the ... | 04/23/1991 |
| 4996661 | Single chip complex floating point numeric processor A pipelined arithmetic processor includes a pair of multipliers in parallel feeding an ALU that, in turn, feeds a pair of parallel accumulators, the various sections being connected by controllable data paths and controlled by a set of pipelined registers... | 02/26/1991 |
