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| Number | Title | Issue Date |
| 7406589 | Processor having efficient function estimate instructions High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instr... | 07/29/2008 |
| 7373369 | Advanced execution of extended floating-point add operations in a narrow dataflow A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the ... | 05/13/2008 |
| 7330864 | System and method for using native floating point microprocessor instructions to manipulate 16-bit floating point data representations A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for conver... | 02/12/2008 |
| 7318014 | Bit accurate hardware simulation in system level simulators A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the system level simulator. These simulations take advantage of the comp... | 01/08/2008 |
| 7287051 | Multi-functional digital signal processing circuitry Multi-functional digital signal processing (“DSP”) circuitry can perform any of a wide range of different DSP functions. For example, the DSP circuitry can perform multiplication of simple or complex numbers of different lengths. The multiplication of simple (i.... | 10/23/2007 |
| 7212959 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 05/01/2007 |
| 7080111 | Floating point multiply accumulator A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accu... | 07/18/2006 |
| 7072929 | Methods and apparatus for efficient complex long multiplication and covariance matrix implementation A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The m... | 07/04/2006 |
| 7062657 | Methods and apparatus for hardware normalization and denormalization Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normali... | 06/13/2006 |
| 7043516 | Reduction of add-pipe logic by operand offset shift The shifters (30, 32) that a floating-point processor (10)'s addition pipeline (14) uses to align or normalize floating-point operands' mantissas before addition or subtraction shift a given mantissa pair one more bit to the left for subtraction... | 05/09/2006 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6748521 | Microprocessor with instruction for saturating and packing data A data processing system is provided with a digital signal processor which has an instruction for saturating multiple fields of a selected set of source operands and storing the separate saturated results in a selected destination register. A first 32-bit operand ( | 06/08/2004 |
| 6748516 | Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. A single DSP instruction includes a pair of sub-instructions: a primary DSP sub-... | 06/08/2004 |
| 6718458 | Method and apparatus for performing addressing operations in a superscalar, superpipelined processor A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform address... | 04/06/2004 |
| 6487653 | Method and apparatus for denormal load handling A microprocessor configured to dynamically switch its floating point load pipeline length from one stage in length to more than one stage in length is disclosed. The microprocessor may perform normal loads and detect denormal loads in a single clock cycle... | 11/26/2002 |
| 6430681 | Digital signal processor In a digital signal processor having an improved arithmetic processing efficiency, there is provided in parallel a first ROM for storing branch commands and a second ROM for storing arithmetic commands. The ROMs are connected to a branch command decoder a... | 08/06/2002 |
| 6317825 | Microprocessor comprising bit concatenation means The invention relates to a microprocessor (MP) comprising means to decode (DEC1) a compact instruction (BMV) for the concatenation of at least one bit (bi) of a first binary word (W1) with at least one bit of a second binary word (W2), and mean... | 11/13/2001 |
| 6088715 | Close path selection unit for performing effective subtraction within a floating point arithmetic unit An optimized multimedia execution unit configured to perform vectored floating point and integer instructions. In one embodiment, the execution unit includes an add/subtract pipeline having far and close data paths. The far data path is configured to hand... | 07/11/2000 |
| 6018756 | Reduced-latency floating-point pipeline using normalization shifts of both operands If the exponents of a floating-point-processor addition pipeline's input operands are equal, a signal (INVERT) that determines whether the pipeline's sole full-width carry-propagate mantissa adder (34) will invert one of its inputs results from an inversi... | 01/25/2000 |
| 5963461 | Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined.... | 10/05/1999 |
| 5905881 | Delayed state writes for an instruction processor An apparatus for and method of providing a data processing system that delays the writing of an architectural state change value to a corresponding architectural state register for a predetermined period of time. This may provide the instruction processor... | 05/18/1999 |
| 5862067 | Method and apparatus for providing high numerical accuracy with packed multiply-add or multiply-subtract operations A method and apparatus for combining at least two packed multiply-accumulate instructions (or equivalent operations) to compute a filter result from coefficients having more bits than can be processed by a single multiply-accumulate instruction (or equiva... | 01/19/1999 |
| 5835392 | Method for performing complex fast fourier transforms (FFT's) A method in a computer system of performing a butterfly stage of a complex fast fourier transform of two input signals. First, a packed multiply add is performed on a first packed complex value generated from a first input signal and a set of trigonometri... | 11/10/1998 |
| 5646875 | Denormalization system and method of operation A system and method for denormalizing a floating point result is disclosed. Denormalized operands are capable of representing much smaller values than can be represented by a number normalized under the ANSI/IEEE standard 754-1985 that governs the represe... | 07/08/1997 |
| 5590365 | Pipeline information processing circuit for floating point operations Disclosed is a pipeline information processing circuit which comprises a register control unit for outputting a plurality of data held in registers at a time; an arithmetic operation unit for carrying out a collective arithmetic operation of a plurality o... | 12/31/1996 |
| 5559977 | Method and apparatus for executing floating point (FP) instruction pairs in a pipelined processor by stalling the following FP instructions in an execution stage A method and apparatus for executing floating-point instruction pairs in a pipelined manner in which exceptions are predicted during an execution stage. In response to a possible exception, the execution pipeline can stall the pipeline. The floating-point... | 09/24/1996 |
| 5530663 | Floating point unit for calculating a compound instruction A+B×C in two cycles A floating point arithmetic unit that executes a single compound instruction that produces the result A+B×C with A, B and C being floating point numbers. Arithmetic on the exponents of A, B and C provide a normalized result of the multiplication before t... | 06/25/1996 |
| 5517438 | Fast multiply-add instruction sequence in a pipeline floating-point processor A pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The reorganization implies th... | 05/14/1996 |
| 5490100 | Cumulative summation unit A summation unit device suitable for the cumulative summation of integer and/or floating point format data presented to an input thereof. The device is particularly useful as an adjunct to a relational database co-processor, receiving data therefrom relat... | 02/06/1996 |
| 5481748 | Method and apparatus for reducing the processing time required to solve numerical problems The invention discloses a method and apparatus for solving a wide range of numerical problems that use N processing elements operating in parallel. To find the solution for a given problem relating to a given function function N points are selected in a determ... | 01/02/1996 |
| 5268854 | Microprocessor with a function for three-dimensional graphic processing A microprocessor includes an integer processing unit with the decimal point fixed; first and second floating point processing units which can execute simultaneously with the integer processing unit; a register file; a first fixed point processing unit for... | 12/07/1993 |
| 5267186 | Normalizing pipelined floating point processing unit A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denor... | 11/30/1993 |
| 5257216 | Floating point safe instruction recognition apparatus A safe instruction recognition method and apparatus for use in a pipelined floating-point processor is described. It is based on the examination of the exponents of each operand. A simple symmetric test, applicable to each exponent, is disclosed using the... | 10/26/1993 |
| 5212662 | Floating point arithmetic two cycle data flow A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an ... | 05/18/1993 |
| 5204829 | Interleaving operations in a floating-point numeric processor A pipelined floating point multiplier is disclosed having the capability of interleaving floating point multiplication with iterative floating point operations (calculations), such as division and square-root taking, by making use of idle stages (pipeline... | 04/20/1993 |
| 5155816 | Pipelined apparatus and method for controlled loading of floating point data in a microprocessor A microprocessor having a pipelined architecture, an onchip data cache, a floating-point unit, a floating-point data latch and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction comprises a fir... | 10/13/1992 |
| 5128888 | Arithmetic unit having multiple accumulators An arithmetic logic unit includes structure for calculating in at least two stages, this structure including substructure for calculating in each of the at least two stages at least partially at the same time and substructure for ensuring the substructure... | 07/07/1992 |
| 5058048 | Normalizing pipelined floating point processing unit A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denor... | 10/15/1991 |
| 5053631 | Pipelined floating point processing unit A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation uni... | 10/01/1991 |
| 5053986 | Circuit for preservation of sign information in operations for comparison of the absolute value of operands A circuit for preserving sign information in a computer system. The computer system is capable of comparing and operating on the absolute value of two operands utilizing a pipelined architecture. Sign information is preserved through the use of a first pl... | 10/01/1991 |
