Bizarre Patents
Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8041758 | Multiplier and arithmetic unit A multiplier has a multiplication array in which partial products are generated by performing multiplication between a multiplier and a multiplicand, and a partial product control circuit which generates an enable signal for activating an effective region in the mul... | 10/18/2011 |
| 8037119 | Multipurpose functional unit with single-precision and double-precision operations A multipurpose arithmetic functional unit selectably performs planar attribute interpolation, unary function approximation, and double-precision arithmetic. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C... | 10/11/2011 |
| 7831652 | Floating point multiplier with embedded status information A system for providing a floating point product comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and ... | 11/09/2010 |
| 7668896 | Data processing apparatus and method for performing floating point multiplication The first and second n-bit significands are multiplied producing a pair of 2n-bit vectors, and half adder logic produces a corresponding plurality of carry and sum bits. A product exponent is checked for correspondence with a predetermined exponent value. A sum oper... | 02/23/2010 |
| 7493357 | Random carry-in for floating-point operations A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operan... | 02/17/2009 |
| 7398289 | Method and device for floating-point multiplication, and corresponding computer-program product In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to ... | 07/08/2008 |
| 7330867 | Method and device for floating-point multiplication, and corresponding computer-program product In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to ... | 02/12/2008 |
| 7294354 | Container with gas release feature A gas release container comprises a container body having a bottom wall and a side wall extending upwardly from the bottom wall and terminating at an upper edge, a removable closure affixed to the upper edge in a substantially gas-tight manner, and a gas release val... | 11/13/2007 |
| 7296049 | Fast multiplication circuits Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier. Generation of a final product is made faster because fewer interstitial pr... | 11/13/2007 |
| 7290024 | Methods and apparatus for performing mathematical operations using scaled integers Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and determines a multiplier value and a scale value based on the scaled-int... | 10/30/2007 |
| 7277540 | Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit... | 10/02/2007 |
| 7240204 | Scalable and unified multiplication methods and apparatus Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2m)) include processing elements arranged to execute in pipeline stages. The pr... | 07/03/2007 |
| 7237216 | Clock gating approach to accommodate infrequent additional processing latencies A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal... | 06/26/2007 |
| 7219117 | Methods and systems for computing floating-point intervals Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first ... | 05/15/2007 |
| 7212959 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 05/01/2007 |
| 7206800 | Overflow detection and clamping with parallel operand processing for fixed-point multipliers A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixe... | 04/17/2007 |
| 7188133 | Floating point number storage method and floating point arithmetic device In order to provide a method or the like for storing floating point numbers to make it easier to manage the floating point numbers using a fixed point processor, when a real number x is represented by a*(2^n) where a mantissa is a and an exponent is n, the mantissa ... | 03/06/2007 |
| 7113593 | Recursive cryptoaccelerator and recursive VHDL design of logic circuits A method and apparatus for performing cryptographic computations employing recursive algorithms to accelerate multiplication and squaring operations. Products and squares of long integer values are recursively reduced to a combination of products and squares reduced... | 09/26/2006 |
| 7111166 | Extending the range of computational fields of integers An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field,... | 09/19/2006 |
| 7080111 | Floating point multiply accumulator A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accu... | 07/18/2006 |
| 7069289 | Floating point unit for detecting and representing inexact computations without flags or traps A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a sep... | 06/27/2006 |
| 7058830 | Power saving in a floating point unit using a multiplier and aligner bypass The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coup... | 06/06/2006 |
| 7039906 | Compiler for enabling multiple signed independent data elements per register A compiler for data processing outputs lower-level code for packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and when executed, the code simultaneously operates on the elements in a register in a singl... | 05/02/2006 |
| 7027598 | Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7027597 | Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7003540 | Floating point multiplier for delimited operands A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the s... | 02/21/2006 |
| 6996596 | Floating-point processor with operating mode having improved accuracy and high performance Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes an operand processing section and an operand flush section. For each... | 02/07/2006 |
| 6988120 | Arithmetic unit and method thereof A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable... | 01/17/2006 |
| 6973471 | Method and apparatus for implementing signed multiplication of operands having differing bit widths without sign extension of the multiplicand A multiplier (42) forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun immediately without being delayed by a sign extension operation. While r... | 12/06/2005 |
| 6922717 | Method and apparatus for performing modular multiplication A method and apparatus for performing modular multiplication is disclosed. An apparatus in accordance with one embodiment of the present invention includes a modular multiplier including a plurality of independent computation channels, where the plurality of indepen... | 07/26/2005 |
| 6922714 | Floating point unit power reduction scheme A system and method for reducing the power consumption of a floating point unit of a processor wherein the processor iteratively performs floating point calculations based upon one or more input operands. The exponential value of a floating point is precalculated wi... | 07/26/2005 |
| 6901503 | Data processing circuits and interfaces An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processo... | 05/31/2005 |
| 6779013 | Floating point overflow and sign detection A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accu... | 08/17/2004 |
| 6697833 | Floating-point multiplier for de-normalized inputs A method is disclosed for efficiently multiplying de-normalized floating-point numbers without necessarily incurring additional delay over the multiplication of normalized numbers, wherein the de-normalized numbers are initially assumed to be normalized. ... | 02/24/2004 |
| 6647404 | Double precision floating point multiplier having a 32-bit booth-encoded array multiplier A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and sum... | 11/11/2003 |
| 6629120 | Method and apparatus for performing a mask-driven interval multiplication operation One embodiment of the present invention provides a system that facilitates performing a mask-driven multiplication operation between arithmetic intervals within a computer system. The system first receives interval operands, including a first interval and... | 09/30/2003 |
| 6606700 | DSP with dual-mac processor and dual-mac coprocessor The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The architecture uses a coupled dual-MAC architecture (MAC1), (MAC2) a... | 08/12/2003 |
| 6490607 | Shared FP and SIMD 3D multiplier A multiplier configured to perform multiplication of both scalar floating point values (X×Y) and packed floating point values (i.e., X1×Y.sub.1 and X2×Y.sub.2). In addition, the multiplier may be configured to calculate X×Y-Z. Th... | 12/03/2002 |
| 6446104 | Double precision floating point multiplier having a 32-bit booth-encoded array multiplier A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and sum... | 09/03/2002 |
| 6370247 | Hash value generating method and device, data encryption method and device, data decryption method and device Hash values, keys and cipher text which have a high degree of data scrambling are generated rapidly. When a message is sent, divisional data of the message are input, and injection extension processing is performed so that the data length of output data i... | 04/09/2002 |
