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| Number | Title | Issue Date |
| 7447725 | Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second ... | 11/04/2008 |
| 7272623 | Methods and apparatus for determining a floating-point exponent associated with an underflow condition or an overflow condition Methods and apparatus are disclosed for determining a floating-point exponent associated with an underflow condition or an overflow condition. The methods and apparatus determine the ‘true’ value of a floating-point exponent based on a truncated value of the flo... | 09/18/2007 |
| 7222146 | Method and apparatus for facilitating exception-free arithmetic in a computer system One embodiment of the present invention provides a system that facilitates performing exception-free arithmetic operations within a computer system. During execution of a computer program, the system receives an instruction to perform an arithmetic operation that in... | 05/22/2007 |
| 7206800 | Overflow detection and clamping with parallel operand processing for fixed-point multipliers A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixe... | 04/17/2007 |
| 7114063 | Condition indicator for use by a conditional branch instruction A branch prediction method and system are provided that accurately predict a branch condition early in an instruction pipeline of a data processing system. By accurately predicting the branch condition, the correct target instruction can be fetched early, thereby av... | 09/26/2006 |
| 7099851 | Applying term consistency to an equality constrained interval global optimization problem One embodiment of the present invention provides a system that solves a global optimization problem specified by a function ƒ and a set of equality constraints q1(x)=0 (i=1, . . . , r), wherein ƒ is a scalar function of a vector x=(x1, x... | 08/29/2006 |
| 7069289 | Floating point unit for detecting and representing inexact computations without flags or traps A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a sep... | 06/27/2006 |
| 7058830 | Power saving in a floating point unit using a multiplier and aligner bypass The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coup... | 06/06/2006 |
| 7016928 | Floating point status information testing circuit A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may sup... | 03/21/2006 |
| 7003540 | Floating point multiplier for delimited operands A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the s... | 02/21/2006 |
| 7003539 | Efficiently determining a floor for a floating-point number An apparatus, method and computer program product for processing a binary floating-point number having a sign bit and a mantissa having a fraction portion. It includes identifying the fraction portion of the binary floating-point number; and replacing each bit of th... | 02/21/2006 |
| 6981012 | Method and circuit for normalization of floating point significants in a SIMD array MPP The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for p... | 12/27/2005 |
| 6976050 | System and method for extracting the high part of a floating point operand A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the determined format is an infinity format or an overflow format. The exponent field bits and the fraction field bits... | 12/13/2005 |
| 6970898 | System and method for forcing floating point status information to selected values A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined for... | 11/29/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6728739 | Data calculating device and method for processing data in data block form A data calculating device preferably used to improve the calculation precision when fixed-point calculation is performed by block-floating-point system. Each piece of data of a data group is calculated, the minimum scale factor representative of the calculate... | 04/27/2004 |
| 6578059 | Methods and apparatus for controlling exponent range in floating-point calculations A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each... | 06/10/2003 |
| 6557021 | Rounding anticipator for floating point operations A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One embodiment of the present invention includes four logic levels, ... | 04/29/2003 |
| 6430677 | Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each... | 08/06/2002 |
| 6219684 | Optimized rounding in underflow handlers The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding mode to generate an underflowed operand. The underflowed o... | 04/17/2001 |
| 6138135 | Propagating NaNs during high precision calculations using lesser precision hardware A floating point arithmetic unit provides consistent propagation of NaNs le performing high precision calculations on hardware designed to perform lower precision calculations. In one embodiment, the floating point arithmetic unit is provided with a micr... | 10/24/2000 |
| 6049865 | Method and apparatus for implementing floating point projection instructions A floating point unit (60) capable of executing projection instructions provides performance improvement in multiple precision floating point arithmetic. The projection instructions provide for obtaining partial sequences of numbers, products, and sums wh... | 04/11/2000 |
| 5966085 | Methods and apparatus for performing fast floating point operations A format for representing floating point numbers reduces the overhead typically associated with parsing floating point numbers and thereby provides for significantly improved processing speeds, particularly for bit-serial processors. According to an exemp... | 10/12/1999 |
| 5943249 | Method and apparatus to perform pipelined denormalization of floating-point results A method of processing a floating-point instruction (including a multiply-add instruction) in a floating-point processor. Prior-art techniques require prenormalization of intermediate results generated by the floating-point processor, but normalization ca... | 08/24/1999 |
| 5894428 | Recursive digital filter A recursive digital filter has a recursive arithmetic operation circuit and an output compensation circuit. The output compensation circuit outputs a value of zero as output data of the recursive digital filter, even if the data input to the recursive ari... | 04/13/1999 |
| 5892697 | Method and apparatus for handling overflow and underflow in processing floating-point numbers A method for processing floating-point numbers, each floating-point number having at least sign portion, an exponent portion and a mantissa portion, comprising the steps of converting a floating-point number memory register representation to a floating-po... | 04/06/1999 |
| 5809292 | Floating point for simid array machine A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein floating point operation is based on block shifts of the fr... | 09/15/1998 |
| 5805487 | Method and system for fast determination of sticky and guard bits A method and system for fast calculation of the sticky bit and a function of the guard bit is disclosed. A first aspect of the method and system provides a fast calculation of the sticky bit. A second aspect provides a fast calculation of a function of th... | 09/08/1998 |
| 5781464 | Apparatus and method for incrementing floating-point numbers represented in diffrent precision modes An incrementer for performing floating-point calculations is capable of incrementing a floating-point number represented in one of several different precision modes. The incrementer includes various incrementer portions coupled to one another and associat... | 07/14/1998 |
| 5619711 | Method and data processing system for arbitrary precision on numbers A data processing system 10 comprises an arbitrary precision number C++ class program code 18, which incorporates arbitrary precision arithmetic. The arbitrary precision number program code 18 resides in a client program 14 and never lose bits of precisio... | 04/08/1997 |
| 5408427 | Detection of exponent underflow and overflow in a floating point adder An exponent subtractor system (226) for a floating point adder (200) generates an exponent result (EXP-- low) and a rounded exponent result (EXP-- high) for an addition operation performed on two floating point numbers and generates ... | 04/18/1995 |
| 5309383 | Floating-point division circuit A floating-point division circuit for performing division on floating-point data using a non-recovery type division method is disclosed. The floating-point division circuit includes a circuit portion for conducting a pre-division processing and pattern de... | 05/03/1994 |
| 5212662 | Floating point arithmetic two cycle data flow A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an ... | 05/18/1993 |
| 5197023 | Hardware arrangement for floating-point addition and subtraction A hardware arrangement for executing floating-point execution of addition and subtraction is supplied with two floating-point numbers each of which includes an exponential, a fraction represented by an absolute value and a sign bit indicating a sign of th... | 03/23/1993 |
| 5027308 | Circuit for adding/subtracting two floating point operands In a floating-point addition (and/or subtraction) of two normalized numbers where a normalized result is also desired, a generation of a carry (overflow) or a borrow from the most significant bit of a minuend operation will cause the resultant mantissa no... | 06/25/1991 |
| 4999802 | Floating point arithmetic two cycle data flow A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and a second floating point arithmetic operation on an oper... | 03/12/1991 |
| 4994996 | Pipelined floating point adder for digital computer A system for subtracting two floating-point binary numbers in a pipelined floating-point adder/subtractor by aligning the two fractions for sustraction; arbitrarily designating the fraction of one of the two floating-point numbers as the subtrahend, and p... | 02/19/1991 |
| 4943940 | Floating point add/subtract and multiplying assemblies sharing common normalization, rounding and exponential apparatus A fully combinatorial floating point arithmetic apparatus is provided comprising separate fully combinatorial add/subtract and multiply assemblies which share a common normalization, rounding and exponential processing apparatus.... | 07/24/1990 |
| 4800516 | High speed floating-point unit In a floating point arithmetic unit, high speed computation is achieved by providing logic for determining whether operands of an instruction have a predetermined condition with respect to the instruction and logic responsive thereto for bypassing selecti... | 01/24/1989 |
| 4788655 | Condition code producing system A condition code producing system for an arithmetic unit which is controlled by a micro program and operate on binary floating point data produces a condition code having a plurality of bits and describing an attribute of the binary floating point data. T... | 11/29/1988 |
