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| Number | Title | Issue Date |
| 7974996 | Math coprocessor A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type sel... | 07/05/2011 |
| 7953784 | Detection of potential need to use a larger data format in performing floating point operations Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or poten... | 05/31/2011 |
| 7917567 | Floating-point processing unit for successive floating-point operations A floating-point processing unit for a succession of floating-point operations. An exponent adjustor is coupled to receive numerical inputs and configured to generate first adjusted values from the numerical inputs. The first adjusted values have equivalent exponent... | 03/29/2011 |
| 7885992 | System and method for implementing irregular data formats A computer system comprises a processing unit configured to process fixed size data words comprising at least one exponent field of variable size and a mantissa of variable size; an input device configured to provide data words to the processing unit; and an output ... | 02/08/2011 |
| 7877431 | Floating point encoding systems and methods Systems and methods for encoding floating point numbers. A system can include encoding logic which encodes invalid floating point representations as valid data. Decoding logic can be used to recognize the invalid floating point representations and map can provide th... | 01/25/2011 |
| 7860914 | Computer system for storing infinite, infinitesimal, and finite quantities and executing arithmetical operations with them In this invention we describe a new type of computer—infinity computer—that is able to operate with infinite, infinitesimal, and finite numbers in such a way that it becomes possible to execute the usual arithmetical operations with all of them. For the new comp... | 12/28/2010 |
| 7676535 | Enhanced floating-point unit for extended functions An embodiment of the present invention is a technique to perform floating-point operations. A floating-point (FP) squarer squares a first argument to produce an intermediate argument. The first and intermediate arguments have first and intermediate mantissas and exp... | 03/09/2010 |
| 7647368 | Data processing apparatus and method for performing data processing operations on floating point data elements Data processing apparatus and method perform data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to de... | 01/12/2010 |
| 7475103 | Efficient check node message transform approximation for LDPC decoder In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A comp... | 01/06/2009 |
| 7461116 | Emulation of a fixed point operation using a corresponding floating point operation A computer is programmed to emulate a fixed-point operation that is normally performed on fixed-point operands, by use of a floating-point operation that is normally performed on floating-point operands. Several embodiments of the just-described computer emulate a f... | 12/02/2008 |
| 7430656 | System and method of converting data formats and communicating between execution units A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to t... | 09/30/2008 |
| 7406589 | Processor having efficient function estimate instructions High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instr... | 07/29/2008 |
| 7397399 | Method and device for transcoding N-bit words into M-bit words with M smaller N The present invention concerns a method for transcoding a N bits word into a M bits word with M | 07/08/2008 |
| 7395296 | Circuitry and method for performing non-arithmetic operations Circuitry is provided for performing a non-arithmetic operation in relation to at least one number. The circuitry includes a first part for carrying out the non-arithmetic operation in relation to the at least one number, the first part providing a result. A second ... | 07/01/2008 |
| 7389499 | Method and apparatus for automatically converting numeric data to a processor efficient format for performing arithmetic operations A compiler (or interpreter) detects source language instructions performing arithmetic operations using a fixed point format (preferably packed decimal). Where the operation can be performed without loss of precision or violation of other constraints of the source l... | 06/17/2008 |
| 7373489 | Apparatus and method for floating-point exception prediction and recovery An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction... | 05/13/2008 |
| 7366748 | Methods and apparatus for fast argument reduction in a computing system There is disclosed method, software and apparatus for evaluating a function f in a computing device using a reduction, core approximation and final reconstruction stage. According to one embodiment of the invention, an argument reduction stage uses an approximate re... | 04/29/2008 |
| 7366749 | Floating point adder with embedded status information A system for providing a floating point sum includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data ... | 04/29/2008 |
| 7363337 | Floating point divider with embedded status information A system for providing floating point division includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and da... | 04/22/2008 |
| 7363471 | Apparatus, system, and method of dynamic binary translation supporting a denormal input handling mechanism A method may translate a set of source instructions into a set of target instructions, execute the set of target instructions, and unmask a denormal input control bit if the set of source instructions uses a denormal input handling mechanism. A method may detect at ... | 04/22/2008 |
| 7352862 | Encryption method, communication system, transmission device, and data input device An encryption method includes the steps of (a) generating random data including a first part and a second part, the first part specifying an operation to be performed on plain text data and the second part being used in the operation, (b) performing the specified op... | 04/01/2008 |
| 7343277 | Parallel computing method for total energy and energy gradient of non experience molecular-orbital method A parallel computing method by using a parallel computer having a plurality of processors is provided, wherein when a 2-electron integration is transformed from an atomic-orbital base (rs|tu) to a molecular-orbital base (ab|cd), indexes r and s of an atomic orbital ... | 03/11/2008 |
| 7340590 | Handling register dependencies between instructions specifying different width registers The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If there is a register dependency between a greater width producer inst... | 03/04/2008 |
| 7330864 | System and method for using native floating point microprocessor instructions to manipulate 16-bit floating point data representations A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for conver... | 02/12/2008 |
| 7324540 | Network protocol off-load engines The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines). ... | 01/29/2008 |
| 7321914 | Fast method for calculating powers of two as a floating point data type A computing system is adapted to calculate an exponent portion of a floating point data type, and is preferably employed in calculating powers of two in a computer language processing environment supporting a union declaration functionality and a left shift function... | 01/22/2008 |
| 7318014 | Bit accurate hardware simulation in system level simulators A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the system level simulator. These simulations take advantage of the comp... | 01/08/2008 |
| 7315932 | Data processing system having instruction specifiers for SIMD register operands and method thereof Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 01/01/2008 |
| 7316007 | Optimization of n-base typed arithmetic expressions A method for arithmetic expression optimization includes receiving a first instruction defined for a first processor having a first base, the first instruction including an operator and at least one operand, converting the first instruction to a second instruction o... | 01/01/2008 |
| 7299170 | Method and apparatus for the emulation of high precision floating point instructions A high precision floating point emulator and associated method for emulating subject program code on a target machine where the subject machine base operands possess a different precision than the target machine. The high precision floating point emulator is provide... | 11/20/2007 |
| 7290024 | Methods and apparatus for performing mathematical operations using scaled integers Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and determines a multiplier value and a scale value based on the scaled-int... | 10/30/2007 |
| 7290020 | Electronic device to calculate and generate linear and non-linear functions Electronic device (10) to calculate linear functions and to calculate and generate non-linear functions, intended to process signals. The electronic device (10) is provided with a calculator unit (11) to calculate linear functions, a device (... | 10/30/2007 |
| 7272623 | Methods and apparatus for determining a floating-point exponent associated with an underflow condition or an overflow condition Methods and apparatus are disclosed for determining a floating-point exponent associated with an underflow condition or an overflow condition. The methods and apparatus determine the ‘true’ value of a floating-point exponent based on a truncated value of the flo... | 09/18/2007 |
| 7242414 | Processor having a compare extension of an instruction set architecture A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision ... | 07/10/2007 |
| 7236999 | Methods and systems for computing the quotient of floating-point intervals Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and... | 06/26/2007 |
| 7228324 | Circuit for selectively providing maximum or minimum of a pair of floating point operands A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point s... | 06/05/2007 |
| 7225323 | Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations.... | 05/29/2007 |
| 7222146 | Method and apparatus for facilitating exception-free arithmetic in a computer system One embodiment of the present invention provides a system that facilitates performing exception-free arithmetic operations within a computer system. During execution of a computer program, the system receives an instruction to perform an arithmetic operation that in... | 05/22/2007 |
| 7219117 | Methods and systems for computing floating-point intervals Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first ... | 05/15/2007 |
| 7212959 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 05/01/2007 |
