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| Number | Title | Issue Date |
| 8145697 | System and method for efficient basis conversion This invention describes a method for evaluating a polynomial in an extension field Fqm, wherein the method comprises the steps of partitioning the polynomial into a plurality of parts, each part is comprised of smaller polynomials using a q | 03/27/2012 |
| 8131794 | RAID system and Galois field product computation method Described is an apparatus for performing a Galois field product computation on data. A first symbol data includes a plurality of symbols each being a bit sequence on which a product operation by a factor α is to be performed in a Galois field, where α is a primiti... | 03/06/2012 |
| 8086656 | System and method for efficient basis conversion This invention describes a method for evaluating a polynomial in an extension field FqM, wherein the method comprises the steps of partitioning the polynomial into a plurality of parts, each part is comprised of smaller polynomials using a q | 12/27/2011 |
| 8015227 | Method in creating a symbol pattern, symbol pattern obtained thereby, method and system for finding a position in such symbol pattern and computer program product for performing the method The invention relates to a method in creating a two-dimensional symbol pattern which may be utilized to determine a position in a large area covered by the pattern, for example for recording handwritten information by means of a pen-like instrument. The invention is... | 09/06/2011 |
| 7930335 | Generic implementations of elliptic curve cryptography using partial reduction A reduction operation is utilized in an arithmetic operation on two binary polynomials X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=tm+am−1tm−1+am−2tm−2+ . . . +a1 | 04/19/2011 |
| 7895253 | Compound Galois field engine and Galois field divider and square root engine and method A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in the Galois field reciprocal generator the first Galois field element by the output of the Galois field reci... | 02/22/2011 |
| 7890565 | Efficient hardware implementation of tweakable block cipher A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T(n+1) basing on known Tn. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed... | 02/15/2011 |
| 7831651 | Method and apparatus for modular inversion for information security and recording medium with a program for implementing the method Values X and N of n bits and a parameter t are input, then Y=X2−t mod N is calculated, then an extended binary GCD algorithm is executed for Y to obtain S=y−12k mod N and k, and R=S2−(k+t=2n) is calculated for S, the... | 11/09/2010 |
| 7805480 | Randomized modular polynomial reduction method and hardware therefor A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates and randomizes a polynomial quotient used for computation of a polynomial remainder. The randomizing error injected into the approximate polyn... | 09/28/2010 |
| 7801937 | Method and apparatus for implementing a look-ahead for low radix Montgomery multiplication A method for performing Montgomery multiplication on n bit numbers includes computing look-ahead partial sum values to generate a Montgomery result after n/2+1 iterations of intermediate result computations. According to one embodiment of the present invention, Mont... | 09/21/2010 |
| 7792893 | Device and method for calculating conversion parameter of montgomery modular multiplication and program therefor A method for calculating a conversion parameter of the Montgomery modular multiplication to improve the efficiency of software installation, comprising a first step for calculating H0=2v×R (mod n) (where v is an integer, v≧1, and (m×k)/v is... | 09/07/2010 |
| 7788311 | Method for fast quotient guess and congruencies manipulation A processor-executed computational method especially for use in cryptographic systems quickly determines a polynomial quotient under specific conditions. For a polynomial modulus f(x), a maximum degree for a polynomial i(x) to be reduced by this method is defined as... | 08/31/2010 |
| 7711763 | Microprocessor instructions for performing polynomial arithmetic operations Polynomial arithmetic instructions are provided in an instruction set architecture (ISA). A multiply-add-polynomial (MADDP) instruction and a multiply-polynomial (MULTP) instruction are provided. ... | 05/04/2010 |
| 7698357 | Modular multiplication with parallel calculation of the look-ahead parameters A device for calculating a multiplication of a multiplier and a multiplicand includes a first performer that performs an exact three operand addition and a second performer that performs an approximated operand addition and a calculator that calculates current look-... | 04/13/2010 |
| 7693927 | Data processing system and method Embodiments of the present invention relate to a data processing system comprising a first arithmetic unit comprising at least one finite field multiplier and at least one finite field adder for selectively performing at least two finite field arithmetic calculation... | 04/06/2010 |
| 7693928 | Galois field linear transformer trellis system A Galois field linear transformer trellis system includes a Galois field linear transformer matrix; an input selection circuit for providing to the matrix a number of input bits in one or more trellis bit streams and a trellis state output of the matrix and a progra... | 04/06/2010 |
| 7668895 | Galois field computation A method and device for computing the multiplicative inverse of element x in Galois field GF(p2m) is proposed. In particular, when p is a prime number and m is an integer, the inverse may be constructed based on the observation that xp | 02/23/2010 |
| 7599979 | Apparatus for hybrid multiplier in GF(2) and method thereof An apparatus and method for hybrid multiplication in GF(2m) by which trade-off between the area and the operation speed of an apparatus for a hybrid multiplier in finite field GF(2m) can be achieved are provided. The apparatus for hybrid multip... | 10/06/2009 |
| 7574469 | Method for generating the multiplicative inverse in a finite field GF(p) The essence of the invention is an effective method for generating the multiplicative inverse in a finite field GF(p) where p is prime, i.e. for generating the modular inverse. This method is derived from the Extended Euclidean Algorithm (EEA). The method is for bin... | 08/11/2009 |
| 7552163 | Montgomery modular multiplier and method thereof A method for power reduction and increasing computation speed for a Montgomery modulus multiplication module for performing modulus multiplication. A coding scheme reduces the hamming distance for partial product and multiple modulus selection, reducing MUX operatio... | 06/23/2009 |
| 7552164 | Accelerated prime sieving using architecture-optimized partial prime product table This embodiment teaches a variation of GCD-based sieving, building tables of prime products, but intentionally restricting the size of table entries to fit within a single machine word. This combination allows one to mix advantages of the two most popular sieves, wh... | 06/23/2009 |
| 7543012 | Method and apparatus to perform squaring operation in finite field A method and apparatus to square an element A when a defining polynomial of a finite field GF(2n) is expressed as f ( x ... | 06/02/2009 |
| 7539719 | Method and apparatus for performing multiplication in finite field GF(2) A method of obtaining C=(c0, . . . , cn−1) of a product of two elements A and B of a finite field GF(2n). The method includes permuting the last d coefficients (an−1, . . . , an−d) of a multiplier A with p... | 05/26/2009 |
| 7526518 | Galois field multiplication system and method A present invention Galois field multiplier system and method utilize lookup tables to generate one partial product term and one feedback term in one clock cycle. In one embodiment, a Galois field multiplier system includes a plurality of shift registers, a pluralit... | 04/28/2009 |
| 7519644 | Finite field serial-serial multiplication/reduction structure and method A method or cryptographic system for communicating securely over an insecure communication channel of the type which communicates a message from a transmitter to a receiver includes the step of providing a finite filed serial-serial multiplication/reduction structur... | 04/14/2009 |
| 7512647 | Condensed Galois field computing system A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial ... | 03/31/2009 |
| 7487194 | Binary and n-valued LFSR and LFCSR based scramblers, descramblers, sequence generators and detectors in Galois configuration N-valued with n≧2 scramblers, descramblers, sequence generators and sequence detectors operate with Linear Feedback Shift Registers (LFSRs) in Galois configuration. Detectors and descramblers in Fibonacci configuration relate to generators and scramblers with LFSR... | 02/03/2009 |
| 7483935 | System and method to implement a matrix multiply unit of a broadband processor The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully... | 01/27/2009 |
| 7464128 | Methods and apparatus for single stage Galois field operations Techniques for single function stage Galois field (GF) computations are described. The new single function stage GF multiplication requires only m-bits per internal logic stage, a savings of m−1 bits per logic stage that do not have to be accounted for as compared... | 12/09/2008 |
| 7426529 | Processor and method for a simultaneous execution of a calculation and a copying process A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in eac... | 09/16/2008 |
| 7424504 | Arithmetic processor for accomodating different field sizes An arithmetic processor is provided, which comprises an arithmetic logic unit (ALU) containing arithmetic circuitry configured to perform field operations in an underlying field. The circuitry comprises a first controller for sequencing the ALU through steps in the ... | 09/09/2008 |
| 7412474 | Montgomery modular multiplier using a compressor and multiplication method A Montgomery modular multiplier receiving a multiplicand (A), a modulus (M), and a multiplier (B), using a t-s compressor, where t>3 and s>1, and a multiplication method performed in the same. In response to a carry propagation adder signal, the t-s compressor perfo... | 08/12/2008 |
| 7404089 | Method and system for protecting against side channel attacks when performing cryptographic operations A method and system for protecting against side channel attacks on cryptographic systems that attempt to recover information from externally detectable signals, such as electromagnetic fields or power input variations. A system operates in accordance with the subjec... | 07/22/2008 |
| 7403965 | Encryption/decryption system for calculating effective lower bits of a parameter for Montgomery modular multiplication An arithmetic device for Montgomery modular multiplication which quickly calculates a parameter ND, the parameter ND satisfying R×R−1−N×ND=1 for an integer N and a radix R that is coprime to and greater than N, with a large number of effective lower... | 07/22/2008 |
| 7403964 | Galois field multiplier array for use within a finite field arithmetic unit A Galois field multiplier array includes a 1st register, a 2nd register, a 3rd register, and a plurality of multiplier cells. The 1st register stores bits of a 1st operand. The 2nd register stores bit... | 07/22/2008 |
| 7395295 | Pipeline core in Montgomery multiplier A multiplier apparatus is arranged for multiplying a first long integer entity with a second long integer entity modulo a prime number. In particular, the comprises a pipelined multiplier core, whilst executing the overall multiplication in Montgomery fashion. ... | 07/01/2008 |
| 7372960 | Method and apparatus for performing finite field calculations In general terms, the invention provides a finite field engine and methods for operating on elements in a finite field. The finite field engine provides finite field sub-engines suitable for any finite field size requiring a fixed number of machine words. The engine... | 05/13/2008 |
| 7373368 | Multiply execution unit that includes 4:2 and/or 5:3 compressors for performing integer and XOR multiplication A multiply execution unit that can generate the integer product of a multiplicand and a multiplier and is also operable to generate the XOR product of the multiplicand and the multiplier. The multiply execution unit includes a summing circuit for summing a plurality... | 05/13/2008 |
| 7364083 | IC card with built-in coprocessor for auxiliary arithmetic, and control method thereof An IC card according to the present invention comprises, a built-in coprocessor for an auxiliary arithmetic in addition to a main arithmetic processing unit, an interval timer for outputting an interrupt request signal upon lapse of a set time shorter than the frame... | 04/29/2008 |
| 7366299 | Method for encrypting and decrypting data using derivative equations and factors A data cryptographer encrypts and decrypts character data of any given length using derivative equations and factors. The use of factors and derivative equations introduces the randomness required for effective encryption without the use of complex mathematics. A se... | 04/29/2008 |
