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| Number | Title | Issue Date |
| 8145696 | Method for representing complex numbers in a communication system A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa... | 03/27/2012 |
| 7917565 | High-speed radix-4 butterfly module and method of performing Viterbi decoding using the same A high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same. The high-speed radix-4 butterfly module includes first to fourth add-compare-select (ACS) circuits. The first and the second ACS circuits receive first to fourth bran... | 03/29/2011 |
| 7685220 | Circular fast fourier transform A Decimation In Frequency (DIF) Fast Fourier Transform (FFT) stage is used in an N bin FFT, wherein N is an even integer. The DIF FFT stage includes swap logic that receives a first input sample, x(v), and a second input sample, x(v+N/2), and selectively supplies ei... | 03/23/2010 |
| 7660840 | Method, system, and computer program product for executing SIMD instruction for flexible FFT butterfly An FFT butterfly instruction based on single instruction multiple data (“SIMD”) technique is executed to reduce the number of cycles for software to perform FFT butterfly operations. The FFT butterfly instruction can implement one or more instances of the FFT bu... | 02/09/2010 |
| 7555512 | RAM-based fast fourier transform unit for wireless communications A wireless communication technique enables fast Fourier transforms (FFTs) and inverse fast Fourier transforms (IFFTs) to be performed with reduced latency and reduced memory requirements. In particular, an FFT/IFFT unit receives input data representative of a commun... | 06/30/2009 |
| 7428564 | Pipelined FFT processor with memory address interleaving A fast Fourier transform processor using a single delay path and a permuter provides a reduction in the implementation area and a related reduction in power consumption through efficiencies obtained by the modification of a butterfly unit and the use of a novel inte... | 09/23/2008 |
| 7391632 | Apparatus of selectively performing fast hadamard transform and fast fourier transform, and CCK modulation and demodulation apparatus using the same A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complex... | 06/24/2008 |
| 7353146 | Block processing of input data in graphical programming environments Methods and systems for performing block processing of input data in graphical programming environments are disclosed. The input data that is to be processed is partitioned into a plurality of blocks. Each block of the input data is applied to the data processing un... | 04/01/2008 |
| 7295939 | Hardware implementation of the pseudo-spectral time-domain method A computer hardware configuration for performing the pseudo-spectral time-domain (PSTD) method on data. The hardware configuration includes a forward fast Fourier transform (FFT) unit that calculates a forward fast Fourier transform (FFT) from the data, and a comple... | 11/13/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7197095 | Inverse fast fourier transform (IFFT) with overlap and add A system for efficiently filtering interfering signals in a front end of a GPS receiver is disclosed. Such interfering signals can emanate from friendly, as well as unfriendly, sources. One embodiment includes a GPS receiver with a space-time adaptive processing (ST... | 03/27/2007 |
| 7197525 | Method and system for fixed point fast fourier transform with improved SNR A system and method of improving signal to noise ration (SNR) in a fixed point fast Fourier transform (FFT/IFFT) generates from sample inputs and a twiddle factor butterfly outputs for each stage; scales the butterfly outputs of this stage from a predicted normaliza... | 03/27/2007 |
| 7164723 | Modulation apparatus using mixed-radix fast fourier transform An FFT (Fast Fourier Transform) processor is disclosed which is a core block of an OFDM (Orthogonal Frequency Division Multiplexing) or DMT (Discrete Multi-tone) MODEM. The FFT processor simultaneously performs sequential input and output by applying an in-place alg... | 01/16/2007 |
| 7154847 | Fast fourier transforming apparatus and method thereof for compensating for OFDM output bit signal A Fast Fourier Transforming apparatus and method thereof for compensating for an OFDM output bit signal is described. The apparatus includes an input buffer unit for storing and outputting a received OFDM bit signal and a butterfly operation unit for performing a bu... | 12/26/2006 |
| 7146395 | Banyan switched processor datapath Data-processing systems including processor datapaths that efficiently support computationally advantageous routing operations are disclosed. Data-processing methods based on such systems are also disclosed. An exemplary data-processing system includes a register fi... | 12/05/2006 |
| 7099909 | Merge and split fast fourier block transform method Fast Fourier Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the Fourier transform domain for enabling recursive merges and splits in Fourier transform domain without data degradation. In... | 08/29/2006 |
| 7099908 | Merge and split generalized block transform method A generalized radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the transform domain enabling recursive merges and splits in transform domain data degradation. Input data in the time domain or spatial doma... | 08/29/2006 |
| 7062522 | Merge and split fast hartley block transform method Fast Hartley Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves for enabling recursive merges and splits in Hartley transform domain without data degradation. Input data in the time domain or s... | 06/13/2006 |
| 7047268 | Address generators for mapping arrays in bit reversed order A method and apparatus to reduce the amount of required memory and instruction cycles when implementing Fast Fourier Transforms (FFTs) on a computer system is described. The invention optimizes FFT software using in-place bit reversal (IPBR) implemented on a process... | 05/16/2006 |
| 7047267 | Merge and split Karhunen-Loeve block transform method Discrete Karhunen-Loeve Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the KLT domain for enabling recursive merges and splits in the KLT domain without data degradation. Input data in t... | 05/16/2006 |
| 7047266 | Merge and split discrete sine block transform method Discrete Sine Transforms in a radix-2 block transform method enables true split and merge transform processing of equal sized data halves in the DST transform domain for enabling recursive merges and splits in DST transform domain without data degradation. Input dat... | 05/16/2006 |
| 7024442 | Processing apparatus A processing apparatus includes a memory capable of storing data, a butterfly arithmetic unit for performing butterfly computation processes, and a bit-reversed order shuffle processing unit for writing results obtained by butterfly computation processes performed b... | 04/04/2006 |
| 7020788 | Reduced power option A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one... | 03/28/2006 |
| 7010558 | Data processor with enhanced instruction execution and method An apparatus and method for performing enhanced algorithmic processing, including reduced cycle-count fast Fourier transform (FFT) calculations. In one aspect, the invention comprises a user-configurable processor having an extension instruction adapted for reduced ... | 03/07/2006 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 02/28/2006 |
| 6976158 | Repeat instruction with interrupt A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruct... | 12/13/2005 |
| 6963892 | Real-time method and apparatus for performing a large size fast fourier transform A method and apparatus for performing a fast Fourier transform (FFT) computation on large data sizes in real time is provided. The speed at which a FFT is performed is increased by reducing the number of times a Direct Memory Access (DMA) unit must transfer data bet... | 11/08/2005 |
| 6957241 | FFT and FHT engine A transformation engine includes an address generator; a butterfly unit coupled to the address generator; a twiddle LUT coupled to the address generator; and a multiplier having a first input coupled to the butterfly unit and a second input coupled to the twiddle LU... | 10/18/2005 |
| 6947961 | Arithmetic unit and receiver unit There are provided an arithmetic unit and a receiver unit which execute an arithmetic operation at a high speed and allow reduction of the size thereof. An input section inputs data of the data group. First to n-th (n>1) storage sections have a capacity capable of s... | 09/20/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6792441 | Parallel multiprocessing for the fast fourier transform with pipeline architecture The discrete Fourier transform (DFT) is computed in a plurality of parallel processors. A DFT of length N is divided into r partial DFTs of length (N/r), in which the r partial DFTs are calculated in separate parallel processors and then combined in a combination ph... | 09/14/2004 |
| 6751643 | Butterfly-processing element for efficient fast fourier transform method and apparatus A Fast Fourier Transformation (FFT) method and apparatus is implemented using a radix-r butterfly design based on a reduced single phase of calculation, termed a butterfly-processing element (BPE). Butterfly calculations are each executed in the same number of itera... | 06/15/2004 |
| 6721708 | Power saving apparatus and method for AC-3 codec by reducing operations The present invention provides a method and apparatus for performing an inverse modified discrete cosine transform (IMDCT) on at least one block of spectral coefficients representing an information signal in the frequency domain. The IMDCT provides an IMDCT output i... | 04/13/2004 |
| 6438568 | Method and apparatus for optimizing conversion of input data to output data The device for converting series of input data elements to series of output data elements is provided with a memory (110) for containing the series of input and output data elements. This memory (110) is embodied so as to successively read a series of inp... | 08/20/2002 |
| 6434583 | Fast fourier transform apparatus and method A apparatus for providing a Fast Fourier Transform (FFT) and an inverse FFT is provided. The apparatus comprises a radix-N core. The radix-N core includes at least N multipliers. The radix-N core also includes a twiddle-factor lookup table that stores com... | 08/13/2002 |
| 6421696 | System and method for high speed execution of Fast Fourier Transforms utilizing SIMD instructions on a general purpose processor A method for performing Fast (forward or inverse) Fourier Transform in a micro-processor-based computer system. The microprocessor includes parallel execution resources for executing parallel floating-point addition, subtractions and multiplication operat... | 07/16/2002 |
| 6366937 | System and method for performing a fast fourier transform using a matrix-vector multiply instruction A system and method that implement a butterfly operation for a fast fourier transform operation in a processor using a matrix-vector-multiply instruction. A first set of inputs to the butterfly operation are defined as r1+j i1 and r2+j i2, and a twiddle f... | 04/02/2002 |
| 6247034 | Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and OFDM receiver and transmitter In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a RAM by a butterfly operation unit in accordance with a RAM address generated by a RAM address g... | 06/12/2001 |
| 6230175 | Reconfigurable digit-serial arithmetic system having a plurality of digit-serial arithmetic units A bus for data transmission, bus switches for slicing the bus, and four arithmetic blocks are provided to perform a series of fixed-point arithmetic operations. Each of the four arithmetic blocks has a plurality of digit-serial arithmetic units, namely a ... | 05/08/2001 |
| 6081821 | Pipelined, high-precision fast fourier transform processor The Fast Fourier Transform (FFT) processor includes a plurality of pipelined, functionally identical stages, each stage adapted to perform a portion of an FFT operation on a block of data. The output of the last stage of the processor is the high-precisio... | 06/27/2000 |
